Re: [PATCH v2 2/3] dt-bindings: riscv: Add Worlds per-hart properties

[Yu-Chien Peter Lin]

Hi all,

On Wed, Jul 29, 2026 at 01:06:59PM -0500, Rob Herring (Arm) wrote:
> 
> On Thu, 30 Jul 2026 00:39:07 +0800, Yu-Chien Peter Lin wrote:
> > Add per-hart DT properties for the RISC-V Worlds architecture:
> > riscv,pmwid, riscv,pmwidlist, and riscv,pmlwidlist. These
> > platform-defined values are primarily used by M-mode firmware
> > to configure World ID CSRs and restrict WID usage across
> > privilege levels.
> > 
> > Also add schema validation rules to enforce valid property
> > combinations based on the ISA extensions present.
> > 
> > Signed-off-by: Yu-Chien Peter Lin <peter.lin@xxxxxxxxxx>
> > ---
> >  .../devicetree/bindings/riscv/cpus.yaml       | 61 +++++++++++++++
> >  .../devicetree/bindings/riscv/worlds.yaml     | 77 +++++++++++++++++++
> >  2 files changed, 138 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/riscv/worlds.yaml
> > 
> 
> My bot found errors running 'make dt_binding_check' on your patch:
> 
> yamllint warnings/errors:
> 
> dtschema/dtc warnings/errors:
> Documentation/devicetree/bindings/cpu/idle-states.example.dtb: cpu@0 (riscv): 'riscv,pmwid' is a required property
> 	from schema $id: http://devicetree.org/schemas/riscv/cpus.yaml
> Documentation/devicetree/bindings/cpu/idle-states.example.dtb: cpu@1 (riscv): 'riscv,pmwid' is a required property
> 	from schema $id: http://devicetree.org/schemas/riscv/cpus.yaml
> Documentation/devicetree/bindings/cpu/idle-states.example.dtb: cpu@10 (riscv): 'riscv,pmwid' is a required property
> 	from schema $id: http://devicetree.org/schemas/riscv/cpus.yaml
> Documentation/devicetree/bindings/cpu/idle-states.example.dtb: cpu@11 (riscv): 'riscv,pmwid' is a required property
> 	from schema $id: http://devicetree.org/schemas/riscv/cpus.yaml

I plan to remove the 'required' check for riscv,pmwid in the next
version. The riscv,pmwid property is intended to provide a valid
fallback when S-domain WID is not specified. This is a platform
integration responsibility, not a schema-enforced constraint.

The next version will only retain prohibitive checks — e.g., if the
smwid extension is absent, riscv,pmwidlist must not be present.

Regards,
Peter Lin