[PATCH v9 07/20] dt-bindings: riscv: add Smcntrpmf ISA extension description

[Atish Patra]

From: Atish Patra <atishp@xxxxxxxxxxxx>

Add the description for Smcntrpmf ISA extension

Acked-by: Rob Herring (Arm) <robh@xxxxxxxxxx>
Signed-off-by: Atish Patra <atishp@xxxxxxxxxxxx>
Link: https://patch.msgid.link/20260701-counter_delegation-v8-7-7909f863a645@xxxxxxxx
Signed-off-by: Paul Walmsley <pjw@xxxxxxxxxx>
---
 Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index ccff2be1224d..eee65cf73d6c 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -181,6 +181,12 @@ properties:
             changes to interrupts as frozen at commit ccbddab ("Merge pull
             request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
 
+        - const: smcntrpmf
+          description: |
+            The standard Smcntrpmf machine-level extension for the machine mode
+            to enable privilege mode filtering for cycle and instret counters as
+            ratified in the 20240326 version of the privileged ISA specification.
+
         - const: smcsrind
           description: |
             The standard Smcsrind machine-level extension extends the

-- 
2.53.0-Meta