[PATCH] rtc: pcf85063: add 1 Hz update interrupt (UIE) support
From: A. Sverdlin
Date: Fri Aug 07 2026 - 08:58:44 EST
From: Alexander Sverdlin <alexander.sverdlin@xxxxxxxxxxx>
The PCF85063A/RV8263 have no dedicated 1 Hz update interrupt, but their
countdown timer can be sourced from a 1 Hz clock (TCF = 1 Hz, T = 1) to
generate a periodic interrupt on the INT pin. Use it to offload UIE to
the hardware, following the pattern of other RTC drivers: the timer is
enabled from set_alarm()/alarm_irq_enable() whenever uie_rtctimer is
active, and the IRQ handler reports RTC_UF when the timer flag (TF) is
set.
RTC_FEATURE_UPDATE_INTERRUPT is now only cleared when no usable interrupt
is wired, preserving the polling emulation for those configurations.
Co-developed-by: Adrian Freihofer <adrian.freihofer@xxxxxxxxxxx>
Signed-off-by: Adrian Freihofer <adrian.freihofer@xxxxxxxxxxx>
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@xxxxxxxxxxx>
---
drivers/rtc/rtc-pcf85063.c | 97 ++++++++++++++++++++++++++++++++++----
1 file changed, 89 insertions(+), 8 deletions(-)
diff --git a/drivers/rtc/rtc-pcf85063.c b/drivers/rtc/rtc-pcf85063.c
index 01e209d88f5f3..76675b75388e4 100644
--- a/drivers/rtc/rtc-pcf85063.c
+++ b/drivers/rtc/rtc-pcf85063.c
@@ -44,6 +44,7 @@
#define PCF85063_REG_CTRL2 0x01
#define PCF85063_CTRL2_AF BIT(6)
#define PCF85063_CTRL2_AIE BIT(7)
+#define PCF85063_CTRL2_TF BIT(3)
#define PCF85063_REG_OFFSET 0x02
#define PCF85063_OFFSET_SIGN_BIT 6 /* 2's complement sign bit */
@@ -63,6 +64,14 @@
#define PCF85063_REG_ALM_S 0x0b
#define PCF85063_AEN BIT(7)
+#define PCF85063_REG_TIMER_VALUE 0x10
+#define PCF85063_REG_TIMER_MODE 0x11
+#define PCF85063_TIMER_MODE_TI_TP BIT(0)
+#define PCF85063_TIMER_MODE_TIE BIT(1)
+#define PCF85063_TIMER_MODE_TE BIT(2)
+#define PCF85063_TIMER_MODE_TCF_MASK GENMASK(4, 3)
+#define PCF85063_TIMER_MODE_TCF_1HZ (2 << 3)
+
struct pcf85063_config {
struct regmap_config regmap;
unsigned has_alarms:1;
@@ -188,12 +197,64 @@ static int pcf85063_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
return 0;
}
+/*
+ * The chip has no dedicated 1 Hz update interrupt. Drive the countdown timer
+ * at 1 Hz to emulate it, so the RTC core can offload UIE to the hardware
+ * instead of polling. A free-running timer is left untouched to preserve its
+ * phase across the per-second re-arming done by the core.
+ */
+static int pcf85063_set_timer_1hz(struct pcf85063 *pcf85063, bool enable)
+{
+ unsigned int mask = PCF85063_TIMER_MODE_TCF_MASK |
+ PCF85063_TIMER_MODE_TIE |
+ PCF85063_TIMER_MODE_TI_TP |
+ PCF85063_TIMER_MODE_TE;
+ unsigned int mode = 0;
+ unsigned int cur;
+ int ret;
+
+ if (enable)
+ mode = PCF85063_TIMER_MODE_TCF_1HZ | PCF85063_TIMER_MODE_TIE |
+ PCF85063_TIMER_MODE_TI_TP | PCF85063_TIMER_MODE_TE;
+
+ ret = regmap_read(pcf85063->regmap, PCF85063_REG_TIMER_MODE, &cur);
+ if (ret)
+ return ret;
+
+ if ((cur & mask) == mode)
+ return 0;
+
+ /* Stop the counter before changing its reload value. */
+ ret = regmap_update_bits(pcf85063->regmap, PCF85063_REG_TIMER_MODE,
+ PCF85063_TIMER_MODE_TE, 0);
+ if (ret)
+ return ret;
+
+ if (enable) {
+ ret = regmap_write(pcf85063->regmap, PCF85063_REG_TIMER_VALUE, 1);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
+ PCF85063_CTRL2_TF, 0);
+ if (ret)
+ return ret;
+ }
+
+ return regmap_update_bits(pcf85063->regmap, PCF85063_REG_TIMER_MODE,
+ mask, mode);
+}
+
static int pcf85063_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
u8 buf[5];
int ret;
+ ret = pcf85063_set_timer_1hz(pcf85063, pcf85063->rtc->uie_rtctimer.enabled);
+ if (ret)
+ return ret;
+
buf[0] = bin2bcd(alrm->time.tm_sec);
buf[1] = bin2bcd(alrm->time.tm_min);
buf[2] = bin2bcd(alrm->time.tm_hour);
@@ -212,22 +273,32 @@ static int pcf85063_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF,
- alrm->enabled ? PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF : PCF85063_CTRL2_AF);
+ pcf85063->rtc->aie_timer.enabled ?
+ PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF : PCF85063_CTRL2_AF);
}
static int pcf85063_rtc_alarm_irq_enable(struct device *dev,
unsigned int enabled)
{
struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
+ int ret;
+
+ ret = pcf85063_set_timer_1hz(pcf85063, pcf85063->rtc->uie_rtctimer.enabled);
+ if (ret)
+ return ret;
return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
PCF85063_CTRL2_AIE,
- enabled ? PCF85063_CTRL2_AIE : 0);
+ pcf85063->rtc->aie_timer.enabled ?
+ PCF85063_CTRL2_AIE : 0);
}
static irqreturn_t pcf85063_rtc_handle_irq(int irq, void *dev_id)
{
struct pcf85063 *pcf85063 = dev_id;
+ unsigned long events = RTC_IRQF;
+ irqreturn_t ret = IRQ_NONE;
+ unsigned int mask = 0;
unsigned int val;
int err;
@@ -236,14 +307,23 @@ static irqreturn_t pcf85063_rtc_handle_irq(int irq, void *dev_id)
return IRQ_NONE;
if (val & PCF85063_CTRL2_AF) {
- rtc_update_irq(pcf85063->rtc, 1, RTC_IRQF | RTC_AF);
- regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
- PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF,
- 0);
- return IRQ_HANDLED;
+ events |= RTC_AF;
+ mask |= PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF;
+ ret = IRQ_HANDLED;
+ }
+
+ if (val & PCF85063_CTRL2_TF) {
+ events |= RTC_UF;
+ mask |= PCF85063_CTRL2_TF;
+ ret = IRQ_HANDLED;
+ }
+
+ if (ret == IRQ_HANDLED) {
+ regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2, mask, 0);
+ rtc_update_irq(pcf85063->rtc, 1, events);
}
- return IRQ_NONE;
+ return ret;
}
static int pcf85063_read_offset(struct device *dev, long *offset)
@@ -607,6 +687,7 @@ static int pcf85063_probe(struct device *dev, struct regmap *regmap, int irq,
dev_warn(&pcf85063->rtc->dev,
"unable to request IRQ, alarms disabled\n");
} else {
+ set_bit(RTC_FEATURE_UPDATE_INTERRUPT, pcf85063->rtc->features);
set_bit(RTC_FEATURE_ALARM, pcf85063->rtc->features);
device_init_wakeup(dev, true);
err = dev_pm_set_wake_irq(dev, irq);
--
2.55.0