Re: [PATCH RESEND 04/17] dt-bindings: soc: spacemit: allow eDP/DP PHY PLL pixel clocks on K3 APMU
From: Rob Herring
Date: Fri Aug 07 2026 - 19:08:36 EST
On Sat, Jul 25, 2026 at 12:51:13AM -0400, Cody Kang wrote:
> The APMU's eDP pixel-clock muxes select the DP PHY PLLs as parents, so the
> K3 syscon takes two clock inputs the other variants do not have.
>
> Gate them behind the K3 compatible instead of widening the shared clock
> list, so a non-K3 syscon cannot silently accept clocks it has no mux for.
>
> Signed-off-by: Cody Kang <codykang.hk@xxxxxxxxx>
> ---
> .../bindings/soc/spacemit/spacemit,k1-syscon.yaml | 30 +++++++++++++++++++++-
> 1 file changed, 29 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml
> index d3a7c93c3c54..b8fc6632a392 100644
> --- a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml
> +++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml
> @@ -31,14 +31,18 @@ properties:
> maxItems: 1
>
> clocks:
> - maxItems: 4
> + minItems: 4
> + maxItems: 6
>
> clock-names:
> + minItems: 4
> items:
> - const: osc
> - const: vctcxo_1m
> - const: vctcxo_3m
> - const: vctcxo_24m
> + - const: edp0_pll_pxclk
> + - const: edp1_pll_pxclk
>
> "#clock-cells":
> const: 1
> @@ -95,6 +99,30 @@ allOf:
> - clocks
> - clock-names
> - "#clock-cells"
> + # Only the K3 APMU exposes the two eDP/DP PHY PLL pixel clocks as extra
> + # inputs (parents of its eDP pixel-clock muxes); every other variant has
> + # the four base oscillator inputs only.
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: spacemit,k3-syscon-apmu
> + then:
> + properties:
> + clocks:
> + minItems: 4
> + maxItems: 6
> + clock-names:
> + minItems: 4
> + maxItems: 6
> + else:
> + properties:
> + clocks:
> + minItems: 4
> + maxItems: 4
> + clock-names:
> + minItems: 4
> + maxItems: 4
4 is already the minimum, so it can be dropped on all of these.
Rob