Re: [PATCH v6 1/1] rust: pci: add extended capability and SR-IOV support

From: Alexandre Courbot

Date: Sat Aug 08 2026 - 22:28:31 EST


On Tue Aug 4, 2026 at 6:11 PM JST, Zhi Wang wrote:
<...>
>> > +/// SR-IOV register layout per PCIe spec (64 bytes starting at cap
>> > offset). +#[repr(C)]
>> > +#[derive(FromBytes, IntoBytes)]
>> > +pub struct ExtSriovRegs {
>> > + /// Extended capability header.
>> > + pub header: u32,
>> > + /// SR-IOV capabilities.
>> > + pub cap: u32,
>> > + /// SR-IOV control.
>> > + pub ctrl: u16,
>> > + /// SR-IOV status.
>> > + pub status: u16,
>> > + /// Initial VFs.
>> > + pub initial_vfs: u16,
>> > + /// Total VFs.
>> > + pub total_vfs: u16,
>> > + /// Number of VFs.
>> > + pub num_vfs: u16,
>> > + /// Function dependency link.
>> > + pub func_dep_link: u8,
>> > + _reserved_0: u8,
>> > + /// First VF offset.
>> > + pub vf_offset: u16,
>> > + /// VF stride.
>> > + pub vf_stride: u16,
>> > + _reserved_1: u16,
>> > + /// VF device ID.
>> > + pub vf_device_id: u16,
>> > + /// Supported page sizes.
>> > + pub supported_page_sizes: u32,
>> > + /// System page size.
>> > + pub system_page_size: u32,
>> > + /// VF BARs (BAR0–BAR5).
>> > + pub vf_bar: [u32; NUM_VF_BARS],
>> > + /// VF migration state array offset.
>> > + pub migration_state: u32,
>> > +}
>>
>> Side-note: It would be interesting if we could end up representing
>> every I/O space this way, although padding and keeping the fields
>> offsets visible would make this challenging. But if we can eventually
>> generalize this, then I guess we can retire the `register!` macro. :)
>>
>
> That sounds interesting idea. :) My understanding is io projection
> covers the operations of the registers but not about the fields in the
> registers. Are you thinking to extend it to cover the register fields
> as well?

Registers are basically bitfields with I/O location information. If you
store a bitfield type in the struct, and use projections to access it,
then you can access the individual fields through the bitfield type.