[PATCH 10/15] dt-bindings: clock: qcom: Add Kuno Global Clock Controller
From: Hardeep Sharma
Date: Sun Aug 09 2026 - 03:29:50 EST
Add the device tree binding and clock/reset IDs for the global clock
controller (GCC) on the Qualcomm Kuno SoC so its device trees can
describe the GCC block and reference the clocks and resets it provides.
Signed-off-by: Hardeep Sharma <hardeep.sharma@xxxxxxxxxxxxxxxx>
---
.../devicetree/bindings/clock/qcom,kuno-gcc.yaml | 56 +++++++++++++
include/dt-bindings/clock/qcom,kuno-gcc.h | 95 ++++++++++++++++++++++
2 files changed, 151 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,kuno-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,kuno-gcc.yaml
new file mode 100644
index 000000000000..ff01ff31c2e2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,kuno-gcc.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,kuno-gcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller on Kuno
+
+maintainers:
+ - Hardeep Sharma <hardeep.sharma@xxxxxxxxxxxxxxxx>
+
+description: |
+ Qualcomm global clock control module provides the clocks and resets on Kuno.
+
+ See also: include/dt-bindings/clock/qcom,kuno-gcc.h
+
+properties:
+ compatible:
+ const: qcom,kuno-gcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Board active-only XO source
+ - description: Sleep clock source
+ - description: PCIe pipe clock source
+
+ power-domains:
+ items:
+ - description: CX domain
+
+required:
+ - compatible
+ - clocks
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+ clock-controller@80000 {
+ compatible = "qcom,kuno-gcc";
+ reg = <0x00080000 0x1f4200>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>,
+ <&pcie_phy>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+...
diff --git a/include/dt-bindings/clock/qcom,kuno-gcc.h b/include/dt-bindings/clock/qcom,kuno-gcc.h
new file mode 100644
index 000000000000..bbaf1799590f
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,kuno-gcc.h
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_KUNO_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_KUNO_H
+
+/* GCC clocks */
+#define GPLL0 0
+#define GPLL0_OUT_EVEN 1
+#define GPLL2 2
+#define GPLL3 3
+#define GPLL4 4
+#define GPLL4_OUT_EVEN 5
+#define GCC_EMAC0_AXI_CLK 7
+#define GCC_EMAC0_PHY_AUX_CLK 8
+#define GCC_EMAC0_PHY_AUX_CLK_SRC 9
+#define GCC_EMAC0_PTP_CLK 10
+#define GCC_EMAC0_PTP_CLK_SRC 11
+#define GCC_EMAC0_RGMII_CLK 12
+#define GCC_EMAC0_RGMII_CLK_SRC 13
+#define GCC_EMAC0_SLV_AHB_CLK 14
+#define GCC_EMAC_0_CLKREF_EN 15
+#define GCC_GP1_CLK 16
+#define GCC_GP1_CLK_SRC 17
+#define GCC_GP2_CLK 18
+#define GCC_GP2_CLK_SRC 19
+#define GCC_GP3_CLK 20
+#define GCC_GP3_CLK_SRC 21
+#define GCC_PCIE_0_CLKREF_EN 22
+#define GCC_PCIE_AUX_CLK 23
+#define GCC_PCIE_AUX_CLK_SRC 24
+#define GCC_PCIE_AUX_PHY_CLK_SRC 25
+#define GCC_PCIE_CFG_AHB_CLK 26
+#define GCC_PCIE_MSTR_AXI_CLK 27
+#define GCC_PCIE_PIPE_CLK 28
+#define GCC_PCIE_PIPE_CLK_SRC 29
+#define GCC_PCIE_RCHNG_PHY_CLK 30
+#define GCC_PCIE_RCHNG_PHY_CLK_SRC 31
+#define GCC_PCIE_SLEEP_CLK 32
+#define GCC_PCIE_SLV_AXI_CLK 33
+#define GCC_PCIE_SLV_Q2A_AXI_CLK 34
+#define GCC_PDM2_CLK 35
+#define GCC_PDM2_CLK_SRC 36
+#define GCC_PDM_AHB_CLK 37
+#define GCC_PDM_XO4_CLK 38
+#define GCC_QUPV3_WRAP0_CORE_2X_CLK 39
+#define GCC_QUPV3_WRAP0_CORE_CLK 40
+#define GCC_QUPV3_WRAP0_S0_CLK 41
+#define GCC_QUPV3_WRAP0_S0_CLK_SRC 42
+#define GCC_QUPV3_WRAP0_S1_CLK 43
+#define GCC_QUPV3_WRAP0_S1_CLK_SRC 44
+#define GCC_QUPV3_WRAP0_S2_CLK 45
+#define GCC_QUPV3_WRAP0_S2_CLK_SRC 46
+#define GCC_QUPV3_WRAP0_S3_CLK 47
+#define GCC_QUPV3_WRAP0_S3_CLK_SRC 48
+#define GCC_QUPV3_WRAP0_S4_CLK 49
+#define GCC_QUPV3_WRAP0_S4_CLK_SRC 50
+#define GCC_QUPV3_WRAP_0_M_AHB_CLK 51
+#define GCC_QUPV3_WRAP_0_S_AHB_CLK 52
+#define GCC_SDCC4_AHB_CLK 53
+#define GCC_SDCC4_APPS_CLK 54
+#define GCC_SDCC4_APPS_CLK_SRC 55
+#define GCC_SNOC_CNOC_USB3_CLK 56
+#define GCC_SYS_NOC_USB_SF_AXI_CLK 57
+#define GCC_USB20_MASTER_CLK 58
+#define GCC_USB20_MASTER_CLK_SRC 59
+#define GCC_USB20_MOCK_UTMI_CLK 60
+#define GCC_USB20_MOCK_UTMI_CLK_SRC 61
+#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 62
+#define GCC_USB20_SLEEP_CLK 63
+#define GCC_USB2_CLKREF_EN 64
+#define GCC_USB3_PRIM_CLKREF_EN 65
+#define GCC_USB_PHY_CFG_AHB2PHY_CLK 66
+#define GCC_BOOT_ROM_AHB_CLK 68
+
+/* GCC resets */
+#define GCC_EMAC0_BCR 0
+#define GCC_PCIE_BCR 1
+#define GCC_PCIE_LINK_DOWN_BCR 2
+#define GCC_PCIE_NOCSR_COM_PHY_BCR 3
+#define GCC_PCIE_PHY_BCR 4
+#define GCC_PCIE_PHY_CFG_AHB_BCR 5
+#define GCC_PCIE_PHY_COM_BCR 6
+#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 7
+#define GCC_PDM_BCR 8
+#define GCC_QUPV3_WRAPPER_0_BCR 9
+#define GCC_QUSB2PHY_BCR 10
+#define GCC_SDCC4_BCR 11
+#define GCC_TCSR_PCIE_BCR 12
+#define GCC_USB20_BCR 13
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR 14
+
+#endif
--
2.43.0