[PATCH 15/15] ARM: dts: qcom: Add initial device tree for Kuno SoC

From: Hardeep Sharma

Date: Sun Aug 09 2026 - 03:35:18 EST

Add SoC-level DTSI (qcom-kuno.dtsi) and IDP board DTS
(qcom-kuno-idp.dts) for the Qualcomm Kuno SoC.

Peripherals included in this initial set:
- Single Cortex-A7 CPU with PSCI idle states
- RPMh RSC with clock controller, power domains, and BCM voter
- GCC (Global Clock Controller)
- TLMM pin controller (110 GPIOs)
- Interconnect (aggre-noc, cnoc-main)
- GENI UART console (QUP SE3)
- SMEM, hardware spinlocks (TCSR mutex)

Signed-off-by: Hardeep Sharma <hardeep.sharma@xxxxxxxxxxxxxxxx>
---
arch/arm/boot/dts/qcom/Makefile | 1 +
arch/arm/boot/dts/qcom/qcom-kuno-idp.dts | 25 ++
arch/arm/boot/dts/qcom/qcom-kuno.dtsi | 423 +++++++++++++++++++++++++++++++
3 files changed, 449 insertions(+)

diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile
index 026d5b682b2b..7327a7b8180e 100644
--- a/arch/arm/boot/dts/qcom/Makefile
+++ b/arch/arm/boot/dts/qcom/Makefile
@@ -26,6 +26,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk07.1-c2.dtb \
qcom-ipq8064-ap148.dtb \
qcom-ipq8064-rb3011.dtb \
+ qcom-kuno-idp.dtb \
qcom-msm8226-microsoft-dempsey.dtb \
qcom-msm8226-microsoft-makepeace.dtb \
qcom-msm8226-microsoft-moneypenny.dtb \
diff --git a/arch/arm/boot/dts/qcom/qcom-kuno-idp.dts b/arch/arm/boot/dts/qcom/qcom-kuno-idp.dts
new file mode 100644
index 000000000000..c2f6650d3fe6
--- /dev/null
+++ b/arch/arm/boot/dts/qcom/qcom-kuno-idp.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+/dts-v1/;
+
+#include "qcom-kuno.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Kuno IDP";
+ compatible = "qcom,kuno-idp", "qcom,kuno";
+
+ aliases {
+ serial0 = &uart3;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart3 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/qcom/qcom-kuno.dtsi b/arch/arm/boot/dts/qcom/qcom-kuno.dtsi
new file mode 100644
index 000000000000..073dda34e188
--- /dev/null
+++ b/arch/arm/boot/dts/qcom/qcom-kuno.dtsi
@@ -0,0 +1,423 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <dt-bindings/clock/qcom,kuno-gcc.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/qcom,rpmhpd.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+
+ pcie_phy: clock-100000000 {
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: clock-32000 {
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ #clock-cells = <0>;
+ };
+
+ xo_board: clock-38400000 {
+ compatible = "fixed-clock";
+ clock-frequency = <38400000>;
+ #clock-cells = <0>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ enable-method = "psci";
+ cpu-idle-states = <&little_cpu_sleep_0>, <&little_cpu_sleep_1>;
+ power-domains = <&cpu_pd0>;
+ power-domain-names = "psci";
+ };
+ };
+
+ domain-idle-states {
+ cluster_sleep_0: cluster-sleep-0 {
+ compatible = "domain-idle-state";
+ idle-state-name = "cx-min";
+ entry-latency-us = <750>;
+ exit-latency-us = <2350>;
+ min-residency-us = <9144>;
+ arm,psci-suspend-param = <0x40000008>;
+ };
+ };
+
+ firmware {
+ scm {
+ compatible = "qcom,scm-kuno", "qcom,scm";
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ little_cpu_sleep_0: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "standalone-pc";
+ entry-latency-us = <350>;
+ exit-latency-us = <450>;
+ min-residency-us = <1774>;
+ arm,psci-suspend-param = <0x40000003>;
+ local-timer-stop;
+ };
+
+ little_cpu_sleep_1: cpu-sleep-1 {
+ compatible = "arm,idle-state";
+ idle-state-name = "pc";
+ entry-latency-us = <550>;
+ exit-latency-us = <750>;
+ min-residency-us = <6700>;
+ arm,psci-suspend-param = <0x40000004>;
+ local-timer-stop;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+
+ cpu_pd0: power-domain-cpu0 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ };
+
+ cluster_pd: power-domain-cluster {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&cluster_sleep_0>;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ quickboot@82100000 {
+ reg = <0x82100000 0x100000>;
+ no-map;
+ };
+
+ aop-image@82200000 {
+ reg = <0x82200000 0x20000>;
+ no-map;
+ };
+
+ aop-cmd-db@82220000 {
+ compatible = "qcom,cmd-db";
+ reg = <0x82220000 0x20000>;
+ no-map;
+ };
+
+ aop-config@82240000 {
+ reg = <0x82240000 0x20000>;
+ no-map;
+ };
+
+ uefi-log@82260000 {
+ reg = <0x82260000 0x10000>;
+ no-map;
+ };
+
+ ipa-fw@82270000 {
+ reg = <0x82270000 0x10000>;
+ no-map;
+ };
+
+ smem@82280000 {
+ compatible = "qcom,smem";
+ reg = <0x82280000 0xc0000>;
+ hwlocks = <&tcsr_mutex 3>;
+ no-map;
+ };
+
+ tme-crashdump@82340000 {
+ reg = <0x82340000 0x40000>;
+ no-map;
+ };
+
+ tme-log@82380000 {
+ reg = <0x82380000 0x4000>;
+ no-map;
+ };
+
+ access-control-db@82384000 {
+ reg = <0x82384000 0x40000>;
+ no-map;
+ };
+
+ secdata@823c4000 {
+ reg = <0x823c4000 0x1000>;
+ no-map;
+ };
+
+ modem-efs@823c5000 {
+ reg = <0x823c5000 0x10000>;
+ no-map;
+ };
+
+ cpucp-fw@82400000 {
+ reg = <0x82400000 0x80000>;
+ no-map;
+ };
+
+ xbl-dt-log@824c0000 {
+ reg = <0x824c0000 0x20000>;
+ no-map;
+ };
+
+ qtee@82500000 {
+ reg = <0x82500000 0x180000>;
+ no-map;
+ };
+
+ trusted-apps@82680000 {
+ reg = <0x82680000 0x600000>;
+ no-map;
+ };
+
+ mpss-audio@82e00000 {
+ reg = <0x82e00000 0x5a00000>;
+ no-map;
+ };
+ };
+
+ soc: soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xffffffff>;
+
+ gcc: clock-controller@80000 {
+ compatible = "qcom,kuno-gcc";
+ reg = <0x00080000 0x1f4200>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>,
+ <&pcie_phy>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ qup0: geniqup@9c0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x009c0000 0x2000>;
+ clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ clock-names = "m-ahb", "s-ahb";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x0 0x1000000>;
+
+ uart3: serial@98c000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0x0 0x0098c000 0x0 0x4000>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&uart_console_active>;
+ pinctrl-1 = <&uart_console_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ status = "disabled";
+ };
+ };
+
+ cnoc_main: interconnect@1580000 {
+ compatible = "qcom,kuno-cnoc-main";
+ reg = <0x01580000 0x19200>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ aggre_noc: interconnect@1640000 {
+ compatible = "qcom,kuno-aggre-noc";
+ reg = <0x01640000 0x33400>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ tcsr_mutex: hwlock@1f40000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0x01f40000 0x40000>;
+ #hwlock-cells = <1>;
+ };
+
+ pdc: interrupt-controller@b220000 {
+ compatible = "qcom,kuno-pdc", "qcom,pdc";
+ reg = <0x0b220000 0x10000>;
+ qcom,pdc-ranges = <1 148 6>,
+ <9 156 2>,
+ <17 164 7>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ };
+
+ restart@c264000 {
+ compatible = "qcom,pshold";
+ reg = <0x0c264000 0x1000>;
+ };
+
+ tlmm: pinctrl@f000000 {
+ compatible = "qcom,kuno-tlmm";
+ reg = <0x0f000000 0x400000>;
+ interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 110>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ uart_console_active: uart-console-active-state {
+ pins = "gpio8", "gpio9";
+ function = "qup0_se3_mira";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ uart_console_sleep: uart-console-sleep-state {
+ pins = "gpio8", "gpio9";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ intc: interrupt-controller@17000000 {
+ compatible = "qcom,msm-qgic2";
+ reg = <0x17000000 0x1000>,
+ <0x17002000 0x1000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ timer@17020000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x17020000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ frame@17021000 {
+ reg = <0x17021000 0x1000>,
+ <0x17022000 0x1000>;
+ frame-number = <0>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ apps_rsc: rsc@17040000 {
+ compatible = "qcom,rpmh-rsc";
+ reg = <0x17040000 0x10000>,
+ <0x17050000 0x10000>,
+ <0x17060000 0x10000>;
+ reg-names = "drv-0",
+ "drv-1",
+ "drv-2";
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ /* drv-1: placeholder (unused) */
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 2>,
+ <SLEEP_TCS 3>,
+ <WAKE_TCS 3>,
+ <CONTROL_TCS 1>;
+ power-domains = <&cluster_pd>;
+
+ rpmhcc: clock-controller {
+ compatible = "qcom,kuno-rpmh-clk";
+ clocks = <&xo_board>;
+ clock-names = "xo";
+ #clock-cells = <1>;
+ };
+
+ rpmhpd: power-controller {
+ compatible = "qcom,kuno-rpmhpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <&rpmhpd_opp_table>;
+
+ rpmhpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmhpd_opp_ret: opp1 {
+ opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+
+ rpmhpd_opp_min_svs: opp2 {
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+
+ rpmhpd_opp_low_svs: opp3 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ rpmhpd_opp_svs: opp4 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ rpmhpd_opp_svs_l1: opp5 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ rpmhpd_opp_nom: opp6 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ rpmhpd_opp_nom_l1: opp7 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ rpmhpd_opp_nom_l2: opp8 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
+ };
+
+ rpmhpd_opp_turbo: opp9 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ rpmhpd_opp_turbo_l1: opp10 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ };
+ };
+ };
+
+ apps_bcm_voter: bcm-voter {
+ compatible = "qcom,bcm-voter";
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};

--
2.43.0