Re: [PATCH v11 00/21] Synopsys DisplayPort Controller improvements for Rockchip platforms

[Alexey Charkov]

Hi Heiko,

On Mon, Aug 10, 2026 at 3:49 PM Heiko Stübner <heiko@xxxxxxxxx> wrote:
>
> Hi Sebastian,
>
> Am Donnerstag, 6. August 2026, 19:02:06 Mitteleuropäische Sommerzeit schrieb Sebastian Reichel:
> > This patch series updates the Synopsys Designware DisplayPort bridge
> > together with the only existing user: The Rockchip RK3576/RK3588:
> >
> >  1. Follow-up bridges (PHY, USB-C connector)
> >     This is needed to get USB-C DP AltMode working; I've followed
> >     the Qualcomm driver as reference
> >
> >  2. Runtime PM
> >     The initial driver has been upstreamed without RPM; add it to
> >     avoid wasting power when nothing is plugged
> >
> >  3. Audio
> >     The initial driver has been upstreamed without audio support;
> >     this adds all missing bits for audio with single stream transport
> >
> > To properly make use of the bridge code the following USBDP PHY series
> > is also needed:
> >
> > https://lore.kernel.org/all/20260714-rockchip-usbdp-cleanup-v13-0-6cb3e769d4c5@xxxxxxxxxxxxx/
>
> I've now had time to test both series (dw-dp + usbdp) :-)
>
> - On my 1080p display I get nice output
> - On my 4K display I get "some" output after increasing the ACLK_VOP to
>   750MHz - although the output itself is garbled. Before there was no
>   output at all

One more thing likely to go wrong on an otherwise unpatched kernel is
dclk. Could you please check what pixel clock your 4K display mode
wants? I bet it's not the 1188 MHz the default PLL configuration
provides.

When my colleagues and I tested a previous iteration of these on over
half a dozen Type-C monitors we could get our hands on, I had to patch
a whole bunch of PLL rates [1] into the table, and reparent the video
port clock driving the DP output to an otherwise unused system PLL
with fractional capability (VPLL in case of RK3576). I'm not yet
trying to upstream those rate changes though, because our prototype
board, which we were testing those on, had signal integrity issues on
two out of four DP pairs, so they need additional testing.

In my experience, any dclk more than 0.1% off the rate required by the
display mode is very likely to produce a blank screen on DP.

Garbled output sounds more like an artifact of an overclocked VOP2 though.

[1] https://github.com/flipperdevices/flipper-linux-kernel/commit/a4c8ce773b069672f0dd4ecb79711bc7d3319b38

Best regards,
Alexey