Re: [PATCH v4 2/8] clk: starfive: Add system-0 domain PLL clock driver

[Changhuang Liang]

Hi, Conor

> On Sat, Aug 08, 2026 at 06:50:48PM -0700, Changhuang Liang wrote:
> > Add system-0 domain PLL clock driver for StarFive JHB100 SoC.
> >
> > Signed-off-by: Changhuang Liang <changhuang.liang@xxxxxxxxxxxxxxxx>
> 
> Could you please get either Hal or someone like Xingyu Wu to review the
> clock driver changes?
> 

Okay, I will ask them to help with the review. 

Best Regards,
Changhuang