[PATCH net-next v7 0/3] dpll: zl3073x: add PTP clock support

From: Ivan Vecera

Date: Tue Aug 11 2026 - 09:50:54 EST


Add PTP hardware clock support to the zl3073x DPLL driver.

Patch 1 scales the poll sleep interval in zl3073x_poll_zero_u8()
proportionally to the timeout to avoid excessive bus traffic for
the longer PTP-related timeouts.

Patch 2 adds low-level channel operations for ToD read/write/adjust,
output phase step, delta frequency offset write and TIE write as
building blocks for PTP callbacks.

Patch 3 registers a PTP clock device for each DPLL channel with
gettimex64, settime64, adjtime, adjfine, adjphase and getmaxphase
callbacks. Callback availability adapts to the current channel
state - adjfine requires NCO pin connected, adjphase uses TIE write
when tracking a reference, and adjtime selects the appropriate
mechanism automatically. Periodic output support will be added in a
follow-up series.

Link: https://lore.kernel.org/netdev/20260807094430.120683-1-ivecera@xxxxxxxxxx/
Link: https://lore.kernel.org/netdev/20260803140637.102339-1-ivecera@xxxxxxxxxx/
Link: https://lore.kernel.org/netdev/20260730132150.371376-1-ivecera@xxxxxxxxxx/
Link: https://lore.kernel.org/netdev/20260713103739.1553284-1-ivecera@xxxxxxxxxx/
Link: https://lore.kernel.org/netdev/20260708170527.916035-1-ivecera@xxxxxxxxxx/

Changes:
v7:
- Check SEM bit before CMD in tod_ready_wait so stale CMD bits
from a prior boot stage do not block ToD operations
- Move ptp_info template assignment from alloc to register to
avoid stale getcycles64 pointers on devlink reload
- Update kernel-doc for tod_ready_wait, adjtime, adjtime_phase_step
and tie_write to match actual return semantics
- Update poll interval changelog to mention effect on all callers
v6:
- Fix kernel-doc warning: move ZL_TOD_MAX_RETRIES define inside
the function body to avoid confusing the kernel-doc parser
v5:
- Add prep patch to scale poll interval with timeout
- Enumerate all ToD commands in tod_ready_wait switch, return
-EOPNOTSUPP with WARN_ON in default case (Vadim)
- Handle CMD=0 (power-on default) in tod_ready_wait
- Rewrite tod_adjust rollover guard as a retry loop that re-reads
until the margin is sufficient, replacing manual fixup and fsleep
- Fix "lowest-ID synth" comments to "first enabled synth"
- Include dev_name() in PTP clock name for multi-device systems
- Update kernel-doc for adjfine/adjphase to document zero no-op
v4:
- Move out_step_time_mask to struct zl3073x_dev (device-global)
- Fix tod_adjust rollover guard for tick-crossing case
- Drop trailing tod_ready_wait from tod_adjust
- Fix TOD_CTRL register item count
- Move phase step registers into existing page 9 section in regs.h
- Align ToD command define values
- Update kernel-doc for chan_state_fetch
- Drop perout support (will rework as follow-up)
- Replace abs(delta) with explicit range check to avoid S64_MIN UB
- Add locking context doc to zl3073x_chan_df_offset_set
- Export zl3073x_chan_tod_ready_wait and wait for ToD completion in
adjtime before phase step/TIE write to prevent WR_NEXT_1HZ from
overwriting the sub-second adjustment
v3:
- Use PTP_1588_CLOCK instead of PTP_1588_CLOCK_OPTIONAL (Jakub)
- Factor out output pin frequency helper to a separate commit (Jakub)
- Remove spurious #include <linux/mutex.h> from dpll.h (Jakub)
v2:
- Squash low-level ops patches (1+3) into patch 1.
- Squash PTP callback patches (2+4) into patch 2, register PTP
clock regardless of initial channel state.

Ivan Vecera (3):
dpll: zl3073x: scale poll interval proportionally to timeout
dpll: zl3073x: add channel ToD, phase step and TIE operations
dpll: zl3073x: add PTP clock support

drivers/dpll/zl3073x/Kconfig | 6 +-
drivers/dpll/zl3073x/chan.c | 325 +++++++++++++++++++++++++-
drivers/dpll/zl3073x/chan.h | 32 +++
drivers/dpll/zl3073x/core.c | 17 +-
drivers/dpll/zl3073x/core.h | 23 ++
drivers/dpll/zl3073x/dpll.c | 439 +++++++++++++++++++++++++++++++++--
drivers/dpll/zl3073x/dpll.h | 5 +
drivers/dpll/zl3073x/regs.h | 52 +++++
8 files changed, 867 insertions(+), 32 deletions(-)


base-commit: b54074ffb813aa4b97585d97ae1ead69d96432b5
--
2.54.0