Re: [PATCH v3] arm64: errata: Add NXP iMX8QM workaround for A53 cache coherency issue

[Peng Fan]

Hi Francesco,
On Mon, Aug 10, 2026 at 04:51:49PM +0200, Francesco Dolcini wrote:
>Hello Peng,
>thanks for the patch, very much appreciated.
>
>On Mon, Aug 03, 2026 at 04:54:44PM +0800, Peng Fan (OSS) wrote:
>> From: Peng Fan <peng.fan@xxxxxxx>
>> 
>> According to NXP errata document IMX8_1N94W[1], the i.MX8QuadMax SoC
>> suffers from a cache coherency issue (ERR050104). The upper bits, above
>> bit 35, of the ARADDR and ACADDR buses within the Arm A53 subsystem
>> have been incorrectly connected. This causes some TLBI and IC
>> maintenance operations exchanged between the A53 and A72 core clusters
>> to be corrupted.
>
>...
>
>> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
>> index 5db8f0619e4b..4ba68c1f29b2 100644
>> --- a/arch/arm64/kernel/cpu_errata.c
>> +++ b/arch/arm64/kernel/cpu_errata.c
>> @@ -200,6 +202,28 @@ cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused)
>>  	sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0);
>>  }
>>  
>> +#ifdef CONFIG_NXP_IMX8QM_ERRATUM_ERR050104
>> +static bool
>> +is_imx8qm_soc(const struct arm64_cpu_capabilities *entry, int scope)
>> +{
>> +	WARN_ON(preemptible());
>> +
>> +	return of_machine_is_compatible("fsl,imx8qm");
>
>fsl,imx8qp is also affected, please adjust

Sure. Let's wait to see more comments for this patch before I post next version.

Thanks
Peng

>
>
>Francesco
>
>
>