[PATCH v4 1/4] dt-bindings: remoteproc: add imx-rproc-psci

[Jiafei Pan]

Add compatible string "fsl,imx-rproc-psci" for i.MX Cortex-A Core's
remoteproc support.

Signed-off-by: Jiafei Pan <Jiafei.Pan@xxxxxxx>

---
Changes in v4:
- Updated description to describe the hardware instead of the binding
- Changed compatible to SoC-specific "fsl,imx93-rproc-psci" with
  generic fallback "fsl,imx-rproc-psci"
- Fixed example node name from "remoteproc-ca55-1" to "remoteproc"

---
 .../remoteproc/fsl,imx-rproc-psci.yaml        | 54 +++++++++++++++++++
 1 file changed, 54 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc-psci.yaml

diff --git a/Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc-psci.yaml b/Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc-psci.yaml
new file mode 100644
index 000000000000..7d0d0da383a2
--- /dev/null
+++ b/Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc-psci.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/remoteproc/fsl,imx-rproc-psci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX Cortex-A Core Remote Processor via PSCI
+
+maintainers:
+  - Jiafei Pan <Jiafei.Pan@xxxxxxx>
+
+description:
+  NXP i.MX SoCs integrate multiple Cortex-A cores. On certain i.MX
+  platforms, one or more of these cores can be offloaded to run RTOS
+  or bare-metal firmware as a remote processor, while the remaining
+  cores run Linux. The cores are powered on and off via PSCI (Power
+  State Coordination Interface) CPU_ON/CPU_OFF calls to the firmware.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - fsl,imx93-ca55-rproc
+      - const: fsl,imx-rproc-psci
+
+  fsl,cpus-mask:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Bitmask indicating which CPU cores are assigned to this remote
+      processor instance. Each bit represents a CPU core, where bit N
+      corresponds to CPU N. For example, 0x2 (0b10) assigns CPU core 1,
+      while 0x6 (0b110) assigns CPU cores 1 and 2.
+
+  memory-region:
+    maxItems: 1
+    description:
+      Phandle to a reserved memory region to be used for the remote
+      processor's code and data.
+
+required:
+  - compatible
+  - fsl,cpus-mask
+  - memory-region
+
+additionalProperties: false
+
+examples:
+  - |
+        remoteproc {
+            compatible = "fsl,imx93-ca55-rproc", "fsl,imx-rproc-psci";
+            /* bitmask: 0b10, assign A55 Core 1 */
+            fsl,cpus-mask = <0x2>;
+            memory-region = <&rtos_ca55_reserved>;
+        };
-- 
2.43.0