Re: [PATCH] KVM: arm64: vgic: Fix detection of MI on no pending LR

[Oliver Upton]

On Mon, 10 Aug 2026 11:29:24 +0100, Kajetan Puchalski wrote:
> As per the ARM GICv3 spec, the maintenance interrupt identified by
> ICH_MISR_EL2.NP is asserted when it is enabled and no List register is
> in pending state. This is further described in the document as "no List
> registers with the State field set to 0b01 (pending)". By checking only
> the pending bit of the LR (bit 62), KVM currently asserts the MI when
> there are no LRs in "pending" or "pending and active" states.
> Fix the detection logic to consider only the "pending" state.
> 
> [...]

Applied to next, thanks!

[1/1] KVM: arm64: vgic: Fix detection of MI on no pending LR
      https://git.kernel.org/kvmarm/kvmarm/c/a342faadc5ac

--
Best,
Oliver