Re: [PATCH v2 8/9] clk: renesas: r9a08g046: Add MIPI DSI and LCDC clock/reset entries

[Geert Uytterhoeven]

On Tue, 11 Aug 2026 at 20:27, Biju <biju.das.au@xxxxxxxxx> wrote:
> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
>
> Add clock and reset entries for the MIPI DSI and LCDC peripherals on the
> RZ/G3L (R9A08G046) SoC.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> ---
> v1->v2:
>  * Replaced M2_DIV7->.m2_div7 as it is internal clock
>  * Added DEF_G3L_LVDS_DIV for fixed factor clock with 4:7 duty cycle.
>  * Prefix mipi_ added for all DSI clks.
>  * Fixed commit header /r9a08g046-cpg/r9a08g046/
>  * Sorted DSI entries.

Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-clk for v7.4.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds