[PATCH] PCI/ASPM: Clear L1SS capability when L1 latency is unacceptable

[Aniket]

From: Aniket Maurya <aniketmaurya@xxxxxxxxxx>

pcie_aspm_cap_init() initializes link->aspm_capable from
link->aspm_support, which includes PCIE_LINK_STATE_L1SS (L1.1, L1.2, etc.)
if supported by both ends of the link.

pcie_aspm_check_latency() then evaluates whether the exit latency of the
link exceeds the acceptable L1 latency advertised by downstream endpoints.
If the latency is unacceptable, it clears PCIE_LINK_STATE_L1 from
link->aspm_capable. However, it does not clear PCIE_LINK_STATE_L1SS.

L1 PM Substates are substates of L1 and require
L1 to be supported and enabled. If L1 is not capable due to unacceptable
exit latency, L1 PM Substates cannot be supported either.

Leaving PCIE_LINK_STATE_L1SS set in link->aspm_capable when L1 is not
capable causes:
1) aspm_ctrl_attrs_are_visible() to expose L1SS sysfs control files
   (e.g., l1_1_aspm, l1_2_aspm) even though the link cannot use L1/L1SS.
2) pcie_config_aspm_link() to unnecessarily invoke pcie_config_aspm_l1ss()
   during ASPM configuration.

Clear PCIE_LINK_STATE_L1SS along with PCIE_LINK_STATE_L1 from
link->aspm_capable when L1 exit latency is unacceptable.

Signed-off-by: Aniket <aniketmaurya@xxxxxxxxxx>
---
 drivers/pci/pcie/aspm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index 172783e7f519..38eb7b1e2377 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -666,7 +666,8 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
 		latency = max_t(u32, latency_up_l1, latency_dw_l1);
 		if ((link->aspm_capable & PCIE_LINK_STATE_L1) &&
 		    (latency + l1_switch_latency > acceptable_l1))
-			link->aspm_capable &= ~PCIE_LINK_STATE_L1;
+			link->aspm_capable &= ~(PCIE_LINK_STATE_L1 |
+						PCIE_LINK_STATE_L1SS);
 		l1_switch_latency += NSEC_PER_USEC;
 
 		link = link->parent;
-- 
2.55.0.766.g2966f0265a-goog