[PATCH 4/4] arm64: dts: renesas: r9a08g046: Add PCIe support
From: Biju
Date: Tue Aug 25 2026 - 05:52:07 EST
From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Populate the previously placeholder PCIe node for the RZ/G3L
(R9A08G046) SoC with interrupts, clocks, resets, interrupt-map, and
the PCIe root port's vendor/device ID, and enable it on the RZ/G3L
SMARC board with the required pin control, CLKREQ# GPIO hog, and
100 MHz reference clock.
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 45 ++++++++++++++++++-
.../boot/dts/renesas/r9a08g046l48-smarc.dts | 16 +++++++
.../boot/dts/renesas/rzg3l-smarc-som.dtsi | 11 +++++
3 files changed, 70 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
index f652ad3f1d1a..83e466ec49ff 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
@@ -1480,20 +1480,61 @@ hsusb1: usb@11eb0000 {
};
pcie: pcie@11e40000 {
+ compatible = "renesas,r9a08g046-pcie";
reg = <0 0x11e40000 0 0x10000>;
ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>;
+ /* Map all possible DRAM ranges (4 GB). */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 1 0x00000000>;
+ bus-range = <0x0 0xff>;
+ interrupts = <GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 484 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "serr", "serr_cor", "serr_nonfatal",
+ "serr_fatal", "axi_err", "inta",
+ "intb", "intc", "intd", "msi",
+ "link_bandwidth", "pm_pme", "dma",
+ "pcie_evt", "msg", "all";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie 0 0 0 0>, /* INTA */
+ <0 0 0 2 &pcie 0 0 0 1>, /* INTB */
+ <0 0 0 3 &pcie 0 0 0 2>, /* INTC */
+ <0 0 0 4 &pcie 0 0 0 3>; /* INTD */
+ clocks = <&cpg CPG_MOD R9A08G046_PCI_ACLK>,
+ <&cpg CPG_MOD R9A08G046_PCI_CLKL1PM>,
+ <&cpg CPG_MOD R9A08G046_PCI_CLK_PMU>;
+ clock-names = "aclk", "pm", "pmu";
+ resets = <&cpg R9A08G046_PCI_ARESETN>;
+ reset-names = "aresetn";
+ power-domains = <&cpg>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
- /* placeholder */
+ renesas,sysc = <&sysc>;
+ status = "disabled";
pcie_port0: pcie@0,0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
ranges;
device_type = "pci";
+ vendor-id = <0x1912>;
+ device-id = <0x0033>;
#address-cells = <3>;
#size-cells = <2>;
- /* placeholder */
};
};
diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
index 5a8269c06435..a155967e1f68 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
@@ -170,6 +170,11 @@ &ohci1 {
status = "okay";
};
+&pcie {
+ pinctrl-0 = <&pcie_pins>;
+ pinctrl-names = "default";
+};
+
&phyrst {
status = "okay";
};
@@ -190,6 +195,17 @@ i2c3_pins: i2c3 {
<RZG3L_PORT_PINMUX(2, 1, 4)>; /* RIIC3_SDA */
};
+ pcie-clkreq-n-hog {
+ gpio-hog;
+ gpios = <RZG3L_GPIO(G, 6) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "PCIE_A_CKREQ";
+ };
+
+ pcie_pins: pcie {
+ pinmux = <RZG3L_PORT_PINMUX(G, 7, 1)>; /* PCIE_RST_OUT# */
+ };
+
rsci1_pins: rsci1 {
pinmux = <RZG3L_PORT_PINMUX(D, 4, 5)>, /* RSCI1_RXD_MISO_SCL */
<RZG3L_PORT_PINMUX(D, 5, 5)>, /* RSCI1_TXD_MOSI_SDA */
diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
index c1c2795bda4e..2ee11d54bd58 100644
--- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
@@ -51,6 +51,12 @@ memory@48000000 {
reg = <0x0 0x48000000 0x0 0x78000000>;
};
+ pcie_refclk: pcie-ref-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
reg_1p0v: regulator-1p0v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.0V";
@@ -190,6 +196,11 @@ phy1: ethernet-phy@7 {
};
};
+&pcie_port0 {
+ clocks = <&pcie_refclk>;
+ clock-names = "ref";
+};
+
&pinctrl {
eth0_pins: eth0 {
txc {
--
2.43.0