[PATCH v6 00/12] ARM: dts: aspeed: anacapa: restructure devicetree for development-phase
From: Colin Huang via B4 Relay
Date: Tue Aug 25 2026 - 06:51:38 EST
This series refactors the Anacapa BMC devicetree layout to better support
development-phase hardware revisions (EVT1/EVT2/DVT) while keeping a platform
entrypoint.
Signed-off-by: Colin Huang <u8813345@xxxxxxxxx>
---
Changes in v6:
- Fold the following fixes into this series:
- Remove redundant vhub pinctrl-names
- Use default SPI2 memory mapping
- Fix dt-check-style strict violations
- Move p3v3_bmc_aux node from evt1.dts to evt2.dts for dt-check-style
- Fix the patch author information
- Link to v5: https://lore.kernel.org/r/20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@xxxxxxxxx
Changes in v5:
- Remove redundant vhub pinctrl-names
- Use default SPI2 memory mapping
- Fix dt-check-style strict violations
- Add Acked-by from Conor Dooley
- Sort compatible strings in alphabetical order
- More commit message for ARM: dts: aspeed: anacapa: Add EVT1 devicetree and point wrapper to it.
- Update commit message to describe both LPDB and RPDB GPIO expanders
- Link to v4: https://lore.kernel.org/r/20260805-anacapa-devlop-phase-devicetree-v4-0-5d67e0efa6c5@xxxxxxxxx
Changes in v4:
- Capitalize the first word of the short description.
- Rework the Anacapa development-phase devicetree hierarchy.
- Ensure that anacapa-evt1 generates an identical devicetree to the existing aspeed-bmc-facebook-anacapa.dts.
- Add SPI flash VCC supply.
- Simplify leakage GPIO line names.
- Add LPDB fuse monitor GPIO expander.
- Link to v3: https://lore.kernel.org/r/20260602-anacapa-devlop-phase-devicetree-v3-0-7c93c5df8d9b@xxxxxxxxx
Changes in v3:
- Restructure the EVT2 devicetree to inherit from the EVT1 devicetree, making it incremental rather than standalone.
- Add the DVT devicetree, inheriting from the EVT2 devicetree.
- Enable MCTP and FRU support for the NIC.
- Align PDB fan GPIO numbering.
- Add an EEPROM device node for the NFC adaptor board.
- Add an additional EEPROM device node for the SCM.
- Add shunt resistor values for HSC monitors
- Link to v2: https://lore.kernel.org/r/20260409-anacapa-devlop-phase-devicetree-v2-0-68f328671653@xxxxxxxxx
Changes in v2:
- Fix dtbs_check fail.
Validated by following command:
make dt_binding_check DT_SCHEMA_FILES=arm/aspeed/aspeed.yaml
make CHECK_DTBS=y DT_SCHEMA_FILES=arm/aspeed/aspeed.yaml aspeed/aspeed-bmc-facebook-anacapa.dtb
make CHECK_DTBS=y DT_SCHEMA_FILES=arm/aspeed/aspeed.yaml aspeed/aspeed-bmc-facebook-anacapa-evt1.dtb
make CHECK_DTBS=y DT_SCHEMA_FILES=arm/aspeed/aspeed.yaml aspeed/aspeed-bmc-facebook-anacapa-evt2.dtb
- Link to v1: https://lore.kernel.org/r/20260407-anacapa-devlop-phase-devicetree-v1-0-97b96367cac3@xxxxxxxxx
---
Andy Chung (1):
ARM: dts: aspeed: anacapa: Enable MCTP and FRU for NIC
Carl Lee (1):
ARM: dts: aspeed: anacapa: Add eeprom device node for NFC adaptor board
Colin Huang (5):
dt-bindings: arm: aspeed: Add Anacapa EVT1 EVT2 DVT board
ARM: dts: aspeed: anacapa: Add EVT1 devicetree and point wrapper to it
ARM: dts: aspeed: anacapa: Add EVT2 devicetree inheriting EVT1
ARM: dts: aspeed: anacapa: Add DVT devicetree inheriting EVT2
ARM: dts: aspeed: anacapa: Add additional EEPROM node for SCM
Peter Shen (1):
ARM: dts: aspeed: anacapa: evt2: Add shunt resistor values for HSC monitors
Rex Fu (4):
ARM: dts: aspeed: anacapa: Align PDB fan GPIO numbering
ARM: dts: aspeed: anacapa: Add LPDB fuse monitor GPIO expander
ARM: dts: aspeed: anacapa: Simplify leakage GPIO line names
ARM: dts: aspeed: anacapa: Add SPI flash VCC supply
.../devicetree/bindings/arm/aspeed/aspeed.yaml | 3 +
.../dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts | 270 +++++
.../aspeed/aspeed-bmc-facebook-anacapa-evt1.dts | 1120 ++++++++++++++++++++
.../aspeed/aspeed-bmc-facebook-anacapa-evt2.dts | 443 ++++++++
.../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 1078 +------------------
5 files changed, 1837 insertions(+), 1077 deletions(-)
---
base-commit: 112264fb0bd0a7982b13da18cd3e289e2ab76eed
change-id: 20260407-anacapa-devlop-phase-devicetree-4101d3f312c0
Best regards,
--
Colin Huang <u8813345@xxxxxxxxx>