Re: [PATCH] ARM: dts: vf500: describe the Cortex-A5 L1 caches

[Frank . Li]

From: Frank Li <Frank.Li@xxxxxxx>


On Mon, 10 Aug 2026 17:22:00 +0200, Mehmet Fide wrote:
> The cpu node carries no cache properties, so cacheinfo has nothing to
> build the hierarchy from and gives up at boot:
>
>   cacheinfo: Unable to detect cache hierarchy for CPU 0
>
> The level and the type of the two L1 caches come from CLIDR and CCSIDR,
> but the geometry does not, so /sys/devices/system/cpu/cpu0/cache is left
> without a size, a line size or a set count.
>
> [...]

Applied to imx/dt64-intend, thanks!

[1/1] ARM: dts: vf500: describe the Cortex-A5 L1 caches
      commit: e148f98ccf9cf71947b6227031fa570c95be4da0

Best regards,
--
Frank Li <Frank.Li@xxxxxxx>