Re: [PATCH] ARM: dts: vf610: describe the L2 cache geometry

[Frank . Li]

From: Frank Li <Frank.Li@xxxxxxx>


On Mon, 10 Aug 2026 17:30:01 +0200, Mehmet Fide wrote:
> The L2 node names the controller and its level, but not its size, line
> size or set count, so cacheinfo cannot describe the last level of the
> hierarchy even though the cpu node already points at it.
>
> Fill them in from the Vybrid reference manual (NXP VFXXXRM), section
> 3.2.3: 8 way set associative, 512 KB, 32 byte line, so 2048 sets.
>
> [...]

Applied to imx/dt64-intend, thanks!

[1/1] ARM: dts: vf610: describe the L2 cache geometry
      commit: a9701a0f76ed7f0b75d7d00c322d13191ef32e7f

Best regards,
--
Frank Li <Frank.Li@xxxxxxx>