Re: [PATCH v9 11/12] arm_mpam: change MPAM-Fb error IRQ to use a threaded IRQ handler
From: Gavin Shan
Date: Wed Aug 26 2026 - 20:10:11 EST
On 8/7/26 8:54 PM, Andre Przywara wrote:
When an MPAM MSC gets into an error condition, it can trigger an errorReviewed-by: Gavin Shan <gshan@xxxxxxxxxx>
IRQ. We cannot really do much about those errors, but we at least query
and log the error, then disable MPAM functionality.
This error report relies on reading the MSC's error status register
(ESR) in the current hard-IRQ handler, which is not possible for MPAM-Fb
based MSC accesses, since they involve mailbox routines that might sleep.
The same is true for clearing the interrupt at the source, which requires
a (potentially sleeping) MSC access as well.
Change the error IRQ handler to be a threaded interrupt, but keep the
handling in the hard-IRQ part for MMIO MSCs. This is needed since the
CPU affinity check in the MSC accessors requires a non-preemptible
context.
When the MSC is using an MPAM-Fb based access, we push the work into the
threaded part of the handler, where the accessors are allowed to sleep.
Also forbid per-CPU interrupts (PPIs) for MPAM-Fb, as we cannot use a
threaded IRQ here.
The actual IRQ handler learns how to deal with errors. We cannot really
handle them, but we can try our best to disable the IRQ anyway.
Should the level IRQ line deactivation fail on the device side, we mask
the IRQ on the irqchip level, to prevent an interrupt storm.
Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx>
---
drivers/resctrl/mpam_devices.c | 77 ++++++++++++++++++++++++++++------
1 file changed, 65 insertions(+), 12 deletions(-)