[PATCH] soc: qcom: smem: Fix byte order in v3 14-frequency parser

[Linmao Li]

smem_dram_parse_v3_14freqs_data() uses the little-endian
freq_khz field directly when scaling the frequency from kHz to Hz. This
produces byte-swapped values on big-endian systems.

Convert freq_khz to CPU byte order before using it, as the other DDR
data parsers do.

Fixes: 1d234eeafc56 ("soc: qcom: smem: Expose DDR data from SMEM")
Signed-off-by: Linmao Li <lilinmao@xxxxxxxxxx>
---
 drivers/soc/qcom/smem_dramc.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/qcom/smem_dramc.c b/drivers/soc/qcom/smem_dramc.c
index 63ebe7f6db590..380746ac18402 100644
--- a/drivers/soc/qcom/smem_dramc.c
+++ b/drivers/soc/qcom/smem_dramc.c
@@ -231,8 +231,11 @@ static void smem_dram_parse_v3_14freqs_data(struct smem_dram *dram, void *data)
 	for (int i = 0; i < MAX_DDR_FREQ_NUM_V3 + 1; i++) {
 		struct ddr_freq_table *freq_entry = &details->ddr_freq_tbl.ddr_freq[i];
 
-		if (freq_entry->freq_khz && freq_entry->enabled)
-			dram->frequencies[dram->num_frequencies++] = 1000 * freq_entry->freq_khz;
+		if (freq_entry->freq_khz && freq_entry->enabled) {
+			u32 freq_khz = le32_to_cpu(freq_entry->freq_khz);
+
+			dram->frequencies[dram->num_frequencies++] = 1000 * freq_khz;
+		}
 	}
 }
 

base-commit: 94d3305d990b055e1561e3b78275344b1f40c86e
-- 
2.25.1