[PATCH 10/11] arm64: dts: qcom: monaco: Disable Inline Crypto Engine by default

[Abel Vesa]

Since UFS_PHY_GDSC is attached to the Inline Crypto Engine and the driver
does not currently enable runtime PM, the GDSC remains enabled while the
device is idle, even on boards where there are no consumers.

So disable the Inline Crypto Engine by default in the SoC DTSI and enable
it only in board DTS files that use it.

Fixes: 68d5d9701a7a ("arm64: dts: qcom: monaco: Add power-domain and iface clk for ice node")
Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxxxxxxxx>
---
 arch/arm64/boot/dts/qcom/monaco-evk.dts   | 4 ++++
 arch/arm64/boot/dts/qcom/monaco.dtsi      | 2 ++
 arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 4 ++++
 3 files changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts
index 9d17ef7d2caf..25980c003a49 100644
--- a/arch/arm64/boot/dts/qcom/monaco-evk.dts
+++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts
@@ -585,6 +585,10 @@ expander6: gpio@3e {
 	};
 };
 
+&ice {
+	status = "okay";
+};
+
 &iris {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index cfe39f923224..e9b807df4a8b 100644
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -2723,6 +2723,8 @@ ice: crypto@1d88000 {
 			clock-names = "core",
 				      "iface";
 			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+
+			status = "disabled";
 		};
 
 		crypto: crypto@1dfa000 {
diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
index 1ff39530ea3d..fbe36a3fc47b 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
+++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
@@ -569,6 +569,10 @@ dsi2dp_bridge_out: endpoint {
 	};
 };
 
+&ice {
+	status = "okay";
+};
+
 &pmm8650au_1_gpios {
 	usb2_en: usb2-en-state {
 		pins = "gpio7";

-- 
2.54.0