[PATCH v2 00/15] drm: starfive: jh7110: Enable display subsystem
From: Michal Wilczynski
Date: Fri Aug 28 2026 - 09:48:53 EST
This series enables the display subsystem on the StarFive JH7110.
The dom_vout block holds the display controller (dc8200), the clock
generator (voutcrg) and the HDMI IP, all inside PD_VOUT. The HDMI IP is
a single register block containing both the controller and the PHY, and
it has a circular clock dependency with voutcrg:
- the HDMI controller needs sys/mclk/bclk from voutcrg
- voutcrg needs the pixel clock for its dc8200 pixel MUXes, and that
clock is generated by the HDMI PHY
The loop only exists if the HDMI block is treated as one device. The
PHY's reference clock is xin24m, not a voutcrg output, so splitting the
node into a parent plus phy and controller children gives deferred probe
a linear order: hdmi-phy, then voutcrg, then hdmi-controller.
The parent maps the register block, owns the regmap its two children
share, and enables the NoC display bus clock and reset that gate the
whole vout region. Each node has its own power-domains property, so
genpd powers PD_VOUT on demand. The RFC's vout-subsystem wrapper is gone
along with the patch that relaxed the voutcrg binding.
Patch 7 adds a .mode_valid platform op to inno-hdmi.
inno_hdmi_bridge_mode_valid() checks the pixel clock against
hdmi->refclk, but that clock only exists where a "ref" clock is
described. The JH7110 gets its pixel clock from the PHY, so refclk is
NULL and the check was skipped: unsupported modes were advertised, the
modeset then "succeeded" because the atomic enable path cannot fail, and
the display stayed blank.
Patches 11-13 drop the PHY duplication from the RFC. The JH7110 has the
same Innosilicon PHY as the RK3328, offset by 0x100 because it sits
behind the controller in the shared register block. Patch 11 factors out
the pre-PLL config format, table lookup, determine_rate, recalc_rate and
the pre-PLL programming; patch 12 moves Rockchip onto it; patch 13 adds
the JH7110 driver. Pixel clock tables, post-PLL and analog config stay
SoC specific.
Patch 12 should be a no-op for Rockchip - same writes, same order, same
values - and RK3228, whose pre-PLL is at different addresses, keeps its
own register code and shares only the lookup. I have no Rockchip
hardware, so it is build tested only (arm and riscv). A Tested-by would
help.
The dc8200 driver, th1520 reset controller and inno-hdmi bridge that the
RFC listed as prerequisites are all upstream now, so there are no
out-of-tree dependencies.
Testing
=======
Tested on a VisionFive 2 v1.3B using modetest.
All 42 modes the sink advertises work, with nothing in dmesg. Pixel
clocks run from 25.175 MHz (640x480@59.94) up to 297 MHz
(4096x2160@30), including 3840x2160 and the full 1920x1080 and 1280x720
rate families.
The four modes the RFC reported as broken work now too: 2560x1440@59.95,
2048x1080@60.00, 2048x1080@24.00 and 720x400@70.08.
Before patch 7, four of the advertised modes failed: 1680x1050@59.95
(146.250 MHz), 1400x1050@59.98 (121.750), 1152x864@59.97 (81.768) and
1280x768@60.35 (80.140). Those pixel clocks are not in the PHY pre-PLL
table, so clk_set_rate() returned -EINVAL and the screen stayed black
while userspace saw a successful modeset. They are rejected in
.mode_valid now; the other refresh rates of those resolutions still work.
Every commit builds for riscv, and the Rockchip PHY also for arm.
Notes
=====
The JH7110 has no central MAINTAINERS entry and maintainership is
fragmented, so patch 15 adds one for the display subsystem and I am
happy to help maintain it. The new PHY library lives under drivers/phy/,
already covered by the generic PHY framework entry.
checkpatch warns "does MAINTAINERS need updating?" on the patches adding
files, because that entry comes in patch 15.
Changes since the RFC:
- Dropped the vout-subsystem wrapper driver and its binding, along with
the patch relaxing the voutcrg binding; genpd handles PD_VOUT per node.
- Renamed the compatible to starfive,jh7110-hdmi-subsystem, dropping
"mfd" as a Linux term (Conor Dooley).
- Absolute $refs in the bindings, unused example labels dropped, and the
examples deduplicated between parent and children (Conor Dooley).
- Added the .mode_valid platform operation (patch 7).
- Split the inno-hdmi rework into a mechanical probe/bind split (patch 4)
and the regmap-from-parent change (patch 5). struct inno_hdmi is no
longer exported; no platform glue dereferences it.
- Replaced the duplicated PHY driver with a shared Innosilicon library
and moved Rockchip onto it (patches 11-13).
- Fixed pre-PLL lock detection, which masked the status read with the
register address instead of the lock bit.
- Fixed a pixel clock refcount underflow: enable returns early on
failure while disable tore down unconditionally.
- voutcrg patch reduced to adding CLK_SET_RATE_PARENT to the two dc8200
pixel MUXes.
- Rebased onto v7.2.
Thanks to Icenowy Zheng for the dc8200 driver and for explaining how the
SoC and the display pipeline fit together.
Thanks also to Dominique Belhachemi, who got rid of the vout-subsystem
wrapper and helped with the testing, and to Graham Markall for testing
the JH7110 display patches independently and writing up the results:
https://big-grey.co.uk/2026/01/26/testing-starfive-jh7110-display-controller-patches/
Link to v1: https://lore.kernel.org/all/20251108-jh7110-clean-send-v1-0-06bf43bb76b1@xxxxxxxxxxx/
---
Michal Wilczynski (15):
dt-bindings: phy: Add starfive,jh7110-inno-hdmi-phy
dt-bindings: display: bridge: Add starfive,jh7110-inno-hdmi-controller
dt-bindings: mfd: Add starfive,jh7110-hdmi-subsystem
drm/bridge: inno-hdmi: Split probe out of bind
drm/bridge: inno-hdmi: Allow the register map to come from a parent
drm/bridge: inno-hdmi: Add .disable platform operation
drm/bridge: inno-hdmi: Add .mode_valid platform operation
soc: starfive: Add jh7110-hdmi-subsystem driver
clk: starfive: jh7110-vout: Allow pixel clock rate propagation
drm/bridge: starfive: Add JH7110 HDMI controller driver
phy: Add common Innosilicon HDMI PHY helpers
phy: rockchip: inno-hdmi: Use the common Innosilicon PHY helpers
phy: starfive: Add jh7110-inno-hdmi-phy driver
riscv: dts: starfive: jh7110: Update DT for display subsystem
MAINTAINERS: Add StarFive JH7110 display subsystem entry
.../starfive,jh7110-inno-hdmi-controller.yaml | 109 ++++
.../mfd/starfive,jh7110-hdmi-subsystem.yaml | 116 +++++
.../phy/starfive,jh7110-inno-hdmi-phy.yaml | 58 +++
MAINTAINERS | 10 +
arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 119 ++++-
arch/riscv/boot/dts/starfive/jh7110.dtsi | 87 +++-
drivers/clk/starfive/clk-starfive-jh7110-vout.c | 4 +-
drivers/gpu/drm/bridge/Kconfig | 11 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/inno-hdmi.c | 82 ++-
drivers/gpu/drm/bridge/jh7110-inno-hdmi.c | 224 ++++++++
drivers/phy/Kconfig | 8 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-inno-hdmi.c | 297 +++++++++++
drivers/phy/rockchip/Kconfig | 1 +
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 127 +----
drivers/phy/starfive/Kconfig | 20 +
drivers/phy/starfive/Makefile | 1 +
drivers/phy/starfive/phy-jh7110-inno-hdmi.c | 567 +++++++++++++++++++++
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile | 1 +
drivers/soc/starfive/Kconfig | 27 +
drivers/soc/starfive/Makefile | 2 +
drivers/soc/starfive/jh7110-hdmi-subsystem.c | 114 +++++
include/drm/bridge/inno_hdmi.h | 10 +-
include/linux/phy/inno-hdmi-phy.h | 85 +++
26 files changed, 1959 insertions(+), 124 deletions(-)
---
base-commit: 8d3ae59288f1e7d58d76558a6ee96d533bc5019f
change-id: 20251031-jh7110-clean-send-7d2242118026
Best regards,
--
Michal Wilczynski <m.wilczynski@xxxxxxxxxxx>