[PATCH] ARM: rockchip: smp: enable CPU1 for rk3066a

[Johan Jonker via B4 Relay]

From: Hüseyin BIYIK <boogiepop@xxxxxxx>

RK3066a CPU1 fails to come online. Fix by using
a similar mailbox construction as in use with
other Rockchip SoCs.

Signed-off-by: Hüseyin BIYIK <boogiepop@xxxxxxx>
Signed-off-by: Johan Jonker <jbx6244@xxxxxxxxx>
---
 arch/arm/mach-rockchip/platsmp.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index f659d894bfae..d7d080c29f3c 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -133,7 +133,8 @@ static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle)
 	if (ret < 0)
 		return ret;
 
-	if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
+	if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9 ||
+	    of_machine_is_compatible("rockchip,rk3066a")) {
 		/*
 		 * We communicate with the bootrom to active the cpus other
 		 * than cpu0, after a blob of initialize code, they will

---
base-commit: 2709dd5ae32f0828f386327c76bba9f39f63a1c6
change-id: 20260829-cpu-c518bde9b473

Best regards,
-- 
Johan Jonker <jbx6244@xxxxxxxxx>