Re: [PATCH 1/2] PCI: dwc: Allow drivers to skip MEM outbound iATU setup

[Niklas Cassel]

On Thu, Aug 27, 2026 at 01:54:47PM +0800, Xincheng Zhang wrote:
> Some DWC-based controllers do not require outbound iATU windows for MEM
> transactions. For those platforms, programming outbound iATU windows for
> host bridge MEM ranges is unnecessary and may constrain the available MEM
> aperture.

Please give a reference to a specific section in a specific version of the
DWC databook.

My guess is that you are relying on the behavior defined in:

DWC EP Databook version 5.96a, section "3.10.5.5 No Address Match Result":
""""
Overview: When there is no address match then the address is untranslated but the TLP header information
(for fields that are programmable) comes from the relevant fields on the application transmit interface
XALI*1.
""""


> 
> Add dw_pcie_rp::bypass_ob_mem_iatu so drivers can skip generic MEM iATU
> setup while using the common DWC host init path.
> 
> Existing drivers keep the current behavior because the flag defaults to
> false. The I/O iATU setup does not use the MEM resource iterator, and the
> iterator may be uninitialized when MEM setup is skipped. Avoid using it in
> the I/O iATU error path.
> 
> Signed-off-by: Xincheng Zhang <zhangxincheng@xxxxxxxxxxxxx>
> ---
>  drivers/pci/controller/dwc/pcie-designware-host.c | 6 +++---
>  drivers/pci/controller/dwc/pcie-designware.h      | 1 +
>  2 files changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index f5a38e6fd8d79..3c5f5ff080818 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -911,7 +911,8 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
>  	resource_list_for_each_entry(entry, &pp->bridge->windows) {
>  		resource_size_t res_size;
>  
> -		if (resource_type(entry->res) != IORESOURCE_MEM)
> +		if (pp->bypass_ob_mem_iatu ||
> +		    resource_type(entry->res) != IORESOURCE_MEM)
>  			continue;

To consider allowing this, at the bare minimum you would have to:

if pp->bypass_ob_mem_iatu is set:

1) Verify that the glue driver has no .cpu_addr_fixup callback defined.

2) For each resource entry that you skip, verify that the atu.parent_bus_addr
is equal to the atu.pci_addr.

Just because pp->bypass_ob_mem_iatu is set in the driver, does not mean that
all device trees for SoCs that is using that driver have defined the PCI range
and the parent CPU range in a way where this would work.


A concrete example:
rk3588 pcie3x4 ranges in v7.0:
https://github.com/torvalds/linux/blob/v7.0/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi#L378

<0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;

PCI address range: 0x900000000-0x93fffffff
parent CPU range:  0x900000000-0x93fffffff


rk3588 pcie3x4 ranges in v6.19:
https://github.com/torvalds/linux/blob/v6.19/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi#L378

<0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;

PCI address range: 0x040000000-0x07fffffff
parent CPU range:  0x900000000-0x93fffffff


E.g. for rk3588, a kernel which has pp->bypass_ob_mem_iatu set in the driver
would work with a device tree from v7.0 and newer, but would send TLPs with
an invalid PCI address when used with a device tree from v6.19 or older.

Since the device tree can be updated independently of the kernel, having this
safety check would be very important IMO.


Kind regards,
Niklas