[PATCH v2 0/3] arm64: dts: intel: fix dw-apb-timer clock initialisation on Stratix10, Agilex and Agilex5

[Adrian Ng Ho Yin]

The DesignWare APB timers on Intel Stratix10, Agilex and Agilex5 SoCs
fail to initialise because their clock managers are platform drivers
registered at core_initcall, which runs after time_init() where
TIMER_OF_DECLARE callbacks fire.  With clocks/clock-names in the DTS,
the timer driver calls clk_get() at a point when the clock provider is
not yet registered, causing the timers to never come up.

Replace the clocks/clock-names reference in the affected DTSIs with a
static clock-frequency of 100 MHz, which is the L4_SP clock rate
configured by the bootloader.  The dw-apb-timer binding explicitly
supports this as an alternative when the clock framework is unavailable
at probe time.

Changelog:
v1 -> v2:
- Add Fixes tags and Cc: stable@xxxxxxxxxxxxxxx to each patch for
  stable backporting.
- Extend the series to socfpga_stratix10.dtsi, which has the same
  TIMER_OF_DECLARE vs clock-manager core_initcall ordering problem.

Adrian Ng Ho Yin (3):
  arm64: dts: socfpga: agilex5: replace clocks reference with
    clock-frequency for dw-apb-timer
  arm64: dts: socfpga: agilex: replace clocks reference with
    clock-frequency for dw-apb-timer
  arm64: dts: socfpga: stratix10: replace clocks reference with
    clock-frequency for dw-apb-timer

 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 12 ++++--------
 arch/arm64/boot/dts/intel/socfpga_agilex.dtsi     | 12 ++++--------
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi    | 12 ++++--------
 3 files changed, 12 insertions(+), 24 deletions(-)

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2.49.GIT