[PATCH v1 2/3] i2c: mlxbf: Use GENMASK()/FIELD_PREP() for GW fields
From: Chris Babroski
Date: Thu Sep 03 2026 - 15:36:05 EST
Replace the explicit shift amounts and rol32() calls used to build the
master and slave gateway control words with GENMASK()/FIELD_PREP().
This makes the field widths explicit and matches the style used
elsewhere in the kernel for register field access.
Also change the single-bit master GW PARSE_EXP and SEND_PEC control
bits to be set with a plain conditional OR instead of rol32(), since
moving a boolean into position via a mask is no longer needed.
Signed-off-by: Chris Babroski <cbabroski@xxxxxxxxxx>
---
drivers/i2c/busses/i2c-mlxbf.c | 30 +++++++++++++++++-------------
1 file changed, 17 insertions(+), 13 deletions(-)
diff --git a/drivers/i2c/busses/i2c-mlxbf.c b/drivers/i2c/busses/i2c-mlxbf.c
index 93fc9f0ba72c..2d2dc234db7a 100644
--- a/drivers/i2c/busses/i2c-mlxbf.c
+++ b/drivers/i2c/busses/i2c-mlxbf.c
@@ -219,7 +219,12 @@
#define MLXBF_I2C_MASTER_BUSY_BIT BIT(30) /* Busy bit. */
#define MLXBF_I2C_MASTER_START_BIT BIT(29) /* Control start. */
#define MLXBF_I2C_MASTER_CTL_WRITE_BIT BIT(28) /* Control write phase. */
+#define MLXBF_I2C_MASTER_WRITE_MASK GENMASK(27, 21) /* Control write bytes */
+#define MLXBF_I2C_MASTER_SEND_PEC_BIT BIT(20) /* Send PEC byte when set to 1 */
#define MLXBF_I2C_MASTER_CTL_READ_BIT BIT(19) /* Control read phase. */
+#define MLXBF_I2C_MASTER_SLV_ADDR_MASK GENMASK(18, 12) /* Slave address */
+#define MLXBF_I2C_MASTER_PARSE_EXP_BIT BIT(11) /* Control parse expected bytes */
+#define MLXBF_I2C_MASTER_READ_MASK GENMASK(10, 4) /* Control read bytes */
#define MLXBF_I2C_MASTER_STOP_BIT BIT(3) /* Control stop. */
#define MLXBF_I2C_MASTER_ENABLE \
@@ -232,12 +237,6 @@
#define MLXBF_I2C_MASTER_ENABLE_READ \
(MLXBF_I2C_MASTER_ENABLE | MLXBF_I2C_MASTER_CTL_READ_BIT)
-#define MLXBF_I2C_MASTER_WRITE_SHIFT 21 /* Control write bytes */
-#define MLXBF_I2C_MASTER_SEND_PEC_SHIFT 20 /* Send PEC byte when set to 1 */
-#define MLXBF_I2C_MASTER_PARSE_EXP_SHIFT 11 /* Control parse expected bytes */
-#define MLXBF_I2C_MASTER_SLV_ADDR_SHIFT 12 /* Slave address */
-#define MLXBF_I2C_MASTER_READ_SHIFT 4 /* Control read bytes */
-
/* SMBus master GW Data descriptor. */
#define MLXBF_I2C_MASTER_DATA_DESC_ADDR 0x80
#define MLXBF_I2C_MASTER_DATA_DESC_SIZE 0x80 /* Size in bytes. */
@@ -288,7 +287,7 @@
#define MLXBF_I2C_SLAVE_ENABLE \
(MLXBF_I2C_SLAVE_BUSY_BIT | MLXBF_I2C_SLAVE_WRITE_BIT)
-#define MLXBF_I2C_SLAVE_WRITE_BYTES_SHIFT 22 /* Number of bytes to write. */
+#define MLXBF_I2C_SLAVE_WRITE_BYTES_MASK GENMASK(28, 22) /* Number of bytes to write. */
#define MLXBF_I2C_SLAVE_SEND_PEC_SHIFT 21 /* Send PEC byte shift. */
/* SMBus slave GW Data descriptor. */
@@ -643,14 +642,19 @@ static int mlxbf_i2c_smbus_enable(struct mlxbf_i2c_priv *priv, u8 slave,
command |= MLXBF_I2C_MASTER_STOP_BIT;
if (read) {
command |= MLXBF_I2C_MASTER_ENABLE_READ;
- command |= rol32(len, MLXBF_I2C_MASTER_READ_SHIFT);
+ command |= FIELD_PREP(MLXBF_I2C_MASTER_READ_MASK, len);
} else {
command |= MLXBF_I2C_MASTER_ENABLE_WRITE;
- command |= rol32(len, MLXBF_I2C_MASTER_WRITE_SHIFT);
+ command |= FIELD_PREP(MLXBF_I2C_MASTER_WRITE_MASK, len);
}
- command |= rol32(slave, MLXBF_I2C_MASTER_SLV_ADDR_SHIFT);
- command |= rol32(block_en, MLXBF_I2C_MASTER_PARSE_EXP_SHIFT);
- command |= rol32(pec_en, MLXBF_I2C_MASTER_SEND_PEC_SHIFT);
+
+ if (block_en)
+ command |= MLXBF_I2C_MASTER_PARSE_EXP_BIT;
+
+ if (pec_en)
+ command |= MLXBF_I2C_MASTER_SEND_PEC_BIT;
+
+ command |= FIELD_PREP(MLXBF_I2C_MASTER_SLV_ADDR_MASK, slave);
/* Clear status bits. */
writel(0x0, priv->mst->io + MLXBF_I2C_SMBUS_MASTER_STATUS);
@@ -1888,7 +1892,7 @@ static int mlxbf_i2c_irq_send(struct mlxbf_i2c_priv *priv, u8 recv_bytes)
/* Prepare control word. */
control32 = MLXBF_I2C_SLAVE_ENABLE;
- control32 |= rol32(write_size, MLXBF_I2C_SLAVE_WRITE_BYTES_SHIFT);
+ control32 |= FIELD_PREP(MLXBF_I2C_SLAVE_WRITE_BYTES_MASK, write_size);
control32 |= rol32(pec_en, MLXBF_I2C_SLAVE_SEND_PEC_SHIFT);
writel(control32, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_GW);
--
2.34.1