Re: [PATCH] loongarch: expose LAMCAS existence via cpuinfo and hwcap

[Rong Bao]

Hi Huacai,


On 2026-09-05 12:46, Huacai Chen wrote:
> [...]
> >          Features                : cpucfg lam lam_bh scq ual fpu lsx lasx
> >          crc32 complex crypto lspw lvz lbt_x86 lbt_arm lbt_mips
> >          Hardware Watchpoint     : yes, iwatch count: 8, dwatch count: 4
> >
> > ... while the CPUCFG 2 instruction reads "0x7e7ccfcf", whose bit 28 is 1,
> > indicating the actual presence of LAMCAS.
> Can we use LAM_CAS in the code, which is similar to LAM_BH?


I originally chose "LAMCAS" and not "LAM_CAS" deliberately to match the 
manual spelling. For example, in "LoongArch Reference Manual, Volume 1 
(version 1.10)"[^0], Table 3 reads as follows:

> 27	LAM_BH	1 indicates support AM{SWAP/ADD}[_DB].{B/H}.
> 28	LAMCAS	1 indicates support AMCAS[_DB].{B/H/W/D}.

Also, in "Toolchain Conventions of the LoongArch(tm) Architecture, 
Version 1.2"[^1], these two extensions are also stylized with different 
hyphenation:

> -mlam-bh	-m[no-]lam-bh	Enable atomic operations 
am{swap/add}[_db].{b/h}.	LoongArch V1.1
> -mlamcas	-m[no-]lamcas	Enable atomic compare-and-swap instructions 
amcas[_db].{b/h/w/d}.	LoongArch V1.1

So I think the name "LAMCAS" maintains the consistency with existing 
specifications and literature better than "LAM_CAS".

> [...] And please use LoongArch in the subject.


Sure. I will fix this in v2.


[^0]: 
https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#the-configuration-information-accessible-by-the-cpucfg-instruction
[^1]: 
https://github.com/loongson/la-toolchain-conventions/blob/36d207cd76301618624d10e67daf7b7f1c060411/LoongArch-toolchain-conventions-EN.adoc?plain=1#L176-L184

--
Regards,
Rong Bao