[PATCH v3 0/2] phy: ti: ti-pipe3: allow configuring ACSPCIe TX/RX mode

[David Oberhollenzer]

This patch set adds a device tree setting to the PIPE3 PHY for
the reference clock selection of the ACSPCIe clock buffer stage.

The clock buffer can operate in either RX mode (clock pins are input,
recover the clock from the bus) or in TX mode (generate the reference
clock for the bus).

This was tested on a board using a phyCORE-AM57x SoM.

Signed-off-by: David Oberhollenzer <david.oberhollenzer@xxxxxxxxxxxxx>

---
Changes in v3:
 - Cleanup device tree property schema

---
Changes in v2:
 - Add ti vendor prefix to property name
 - Reorder patch set to add the device tree documentation first
 - Add a property description to the device tree schema
 - Add an example to the device tree documentation
 - Make the property exclusive to the PCIe PHY in the device tree schema

---
Sashiko:
 - syscon_regmap_lookup_by_phandle_args() does not return -EPROBE_DEFER,
   there is no broken probe deferral here
 - logging but ignoring a failure of ti_pipe3_acspcie_tx_rx_mode() is
   intentional, following implementations of related properties,
   e.g. dra7xx_pcie_unaligned_memaccess()

---

David Oberhollenzer (2):
  dt-bindings: phy: ti,phy-usb3: Add aspcie reference clock setting
  phy: ti: ti-pipe3: allow configuring ACSPCIe TX/RX mode

 .../devicetree/bindings/phy/ti,phy-usb3.yaml  | 38 +++++++++++++++++++
 drivers/phy/ti/phy-ti-pipe3.c                 | 27 +++++++++++++
 2 files changed, 65 insertions(+)

-- 
2.55.0