Re: [PATCH RESEND v4 0/3] x86/apic: Add support for additional AMD EILVT registers

[Bharata B Rao]

On 03-Sep-26 2:58 PM, Naveen N Rao (AMD) wrote:
> Add support for additional APIC EILVT registers being introduced in 
> future AMD processors:
> https://docs.amd.com/v/u/en-US/69205_1.00_AMD64_IBS_PUB)
> 
> This is a resend of v4, rebased on tip/master. Previous posting:
> http://lore.kernel.org/r/cover.1784785046.git.naveen@xxxxxxxxxx

This change is required by IBS memory profiler as well which is being posted as
one of the hotness sources in pghot patchset
(https://lore.kernel.org/linux-mm/20260728054356.291998-1-bharata@xxxxxxx/)

Tested this series with pghot+ibs memory profiler.

For the series, Tested-by: Bharata B Rao <bharata@xxxxxxx>

Regards,
Bharata.