Re: [PATCH v6 05/17] iio: adc: Add AD7768 and AD7768-4 core support

[Janani Sunil]

On 9/6/26 10:34, Andy Shevchenko wrote:
> On Fri, Sep 04, 2026 at 04:14:57PM +0200, Janani Sunil wrote:
> > Add core support for the AD7768 and AD7768-4 simultaneous sampling ADCs.
> > Configure supplies, clock and reset, use a custom regmap bus for the SPI
> > protocol, and parse the enabled channels and input buffer settings from
> > devicetree.
> >
> > Connect the converter to an IIO backend for buffered capture with CRC,
> > provide a fixed safe wideband sampling configuration and add runtime
> > power management.
> ...
>
> > +	/*
> > +	 * DCLK(min) is ODR * channels per DOUTx * 32. With fast mode
> > +	 * (fMOD = MCLK / 4) and x64 decimation, this gives:
> > +	 * MCLK / DCLK = 8 * data lines / channels.
> > +	 */
> > +	dclk_div = 8 * st->datalines / st->chip_info->num_channels;
> > +	dclk_div_reg = AD7768_INTERFACE_CFG_DCLK_DIV(dclk_div);
> So, this one is (4 - ffs(dclk_div)). If num_channels == 1, this will always give 0.
> If num_channels == 2, this might give 0, 8, ... Since ffs(0) implementation is defined
> to return 0, this will return... 0! So, tell me how this code may return
> anything than 0?

The st->chip_info->num_channels is fixed at either 8 (AD7768) or 4 (AD7768-4) and not the number of channels described in the firmware. The supported dataline configurations produce dclk_div of 1, 2 or 8 and register values of 3, 2 or 0.
However, I agree that using the ffs() obscures this mapping, so I will replace it with an explicit switch over the supported divider values.

Regards,
Jan