Re: [PATCH v2] PCI: Disable not supported reset methods on DG1 0x4905

[Janusz Krzysztofik]

On Tue, 2026-09-08 at 13:46 +0300, Ville Syrjälä wrote:
> On Mon, Sep 07, 2026 at 10:59:18AM +0200, Janusz Krzysztofik wrote:
> > DRM CI consistently reports failing device reset attempts on Intel DG1
> > discrete graphics adapters.  Manual reproduction attempts allowed to
> > narrow down the scope of that problem to a specific revision of that
> > hardware, SKU 8086:4905.  It has been confirmed that both reset methods
> > claimed by the device, i.e., flr and bus, suffer from that issue.
> 
> IIRC the documented workaround for the issue is some kind of magic
> register write after the FLR to unblock some internal state machine,
> but the CPU isn't allowed to do that write and instead it has to be
> performed by the GuC. That means we'd somehow have to reinitialize
> the GuC very early after the FLR, which sounds rather difficult.
> 

Hmm, maybe i915 initialization order could be re-arranged to apply that 
workaround via GuC before touching the blocked hardware.  If that was 
possible then maybe we only needed to use a PCI quirk to block consecutive 
FLRs before the workaround is applied in order to prevent a hardware 
freeze.

I'm adding Daniele to the loop.

Thanks,
Janusz

> > 
> > Since consecutively failing device resets may lead to system hangs,
> > disable both useless reset methods.  A respective CI test will then be
> > skipped instead of aborting whole CI jobs.
> > 
> > Suggested-by: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx>
> > Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/work_items/11814
> > Reviewed-by: Andi Shyti <andi.shyti@xxxxxxxxxxxxxxx>
> > Reviewed-by: Krzysztof Karas <krzysztof.karas@xxxxxxxxx>
> > Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik@xxxxxxxxxxxxxxx>
> > ---
> > v2: Fix commit description wording (Andi)
> >   - add Suggested-by: tag missing from v1,
> >   - add collected Reviewed-by: tags.
> > 
> >  drivers/pci/quirks.c | 5 +++++
> >  1 file changed, 5 insertions(+)
> > 
> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> > index de9bbccda21fd..e55475374c6fd 100644
> > --- a/drivers/pci/quirks.c
> > +++ b/drivers/pci/quirks.c
> > @@ -3811,6 +3811,9 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset);
> >   */
> >  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1164, quirk_no_bus_reset);
> >  
> > +/* Intel DG1 0x4905 may not recover from bus reset */
> > +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4905, quirk_no_bus_reset);
> > +
> >  static void quirk_no_pm_reset(struct pci_dev *dev)
> >  {
> >  	/*
> > @@ -5597,6 +5600,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
> >   * AMD Neural Processing Unit 0x1502 0x17f0
> >   * Intel 82579LM Gigabit Ethernet Controller 0x1502
> >   * Intel 82579V Gigabit Ethernet Controller 0x1503
> > + * Intel DG1 Discrete Graphics Adapter 0x4905
> >   * Mediatek MT7922 802.11ax PCI Express Wireless Network Adapter
> >   * Mediatek MT7925 802.11be PCI Express Wireless Network Adapter
> >   */
> > @@ -5612,6 +5616,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1502, quirk_no_flr);
> >  DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x17f0, quirk_no_flr);
> >  DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr);
> >  DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr);
> > +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x4905, quirk_no_flr);
> >  DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MEDIATEK, 0x0616, quirk_no_flr);
> >  DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MEDIATEK, 0x7925, quirk_no_flr);
> >  
> > -- 
> > 2.54.0