[PATCH 19/34] arm64: dts: qcom: kodiak: Fix PCIe wake GPIO polarity
From: Krishna Chaitanya Chundru
Date: Thu Sep 10 2026 - 10:31:50 EST
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>
Reviewed-by: Manivannan Sadhasivam <mani@xxxxxxxxxx>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts | 3 ++-
arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 4 ++--
arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts | 4 ++--
arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts | 2 +-
arch/arm64/boot/dts/qcom/qcs6490-vicharak-axon-mini.dts | 4 ++--
5 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts
index 5bb33a8a9830..509fc4941a02 100644
--- a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts
+++ b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts
@@ -558,7 +558,7 @@ &pcie0_phy {
&pcie0_port {
reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
};
&pcie1 {
@@ -579,6 +579,7 @@ &pcie1_phy {
&pcie1_port0 {
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
};
&pmk8350_adc_tm {
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
index 41d60c87f5bd..ed0b81710b9a 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
@@ -541,7 +541,7 @@ &pcie0_phy {
&pcie0_port {
reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
};
&pcie1 {
@@ -571,7 +571,7 @@ &pcie1_phy {
&pcie1_port0 {
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
};
&pm7325_gpios {
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts
index 31bafa2cf51d..6527cf815b85 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts
@@ -705,7 +705,7 @@ &pcie0_phy {
&pcie0_port {
reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
};
&pcie1 {
@@ -736,7 +736,7 @@ &pcie1_phy {
&pcie1_port0 {
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
pcie@0,0 {
compatible = "pci1179,0623";
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts
index 13e8e62f6205..4ac2998a0a6a 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts
@@ -833,7 +833,7 @@ &pcie0_phy {
&pcie0_port {
reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
};
&pcie1 {
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-vicharak-axon-mini.dts b/arch/arm64/boot/dts/qcom/qcs6490-vicharak-axon-mini.dts
index 4f2e0109f49b..141d263e6566 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-vicharak-axon-mini.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-vicharak-axon-mini.dts
@@ -653,7 +653,7 @@ &ice {
&pcie0 {
perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>;
pinctrl-names = "default";
@@ -670,7 +670,7 @@ &pcie0_phy {
&pcie1 {
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>;
pinctrl-names = "default";
--
2.34.1