Re: [PATCH v24 04/15] mmc: renesas_sdhi: Add max_divider field to support SoC-specific clock ranges

[wsa+renesas]

> > > -	mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L);
> > > +	mmc->f_min = max(clk_round_rate(priv->clk, 1) /
> > > +host->pdata->max_divider, 1L);
> > 
> > ... because the existing code is just too subtle / fragile and hard to understand. I think we should move
> > clk_round_rate() out of max() and handle it seperatly before. What do you think?
> 
> You mean use, max(clk_get_rate(priv->clk) / 512, 1);
> 
> clk_get_rate() returns unsigned long compared to clk_round_rate() which return long??

I mean

	rate = clk_round_rate(priv->clk, 1);
	if (rate < 0)
		...
	mmc->f_min = max(rate / host->pdata->max_divider, 1L);

Makes sense?

Attachment: signature.asc
Description: PGP signature