RE: [PATCH v2 2/3] phy: add AST2700 usb3.2 phy driver

[Ryan Chen]

> Subject: RE: [PATCH v2 2/3] phy: add AST2700 usb3.2 phy driver
> 
> 
> > Subject: Re: [PATCH v2 2/3] phy: add AST2700 usb3.2 phy driver
> >
> > On Wed, 2026-07-15 at 05:55 +0000, Ryan Chen wrote:
> > >
> > > >
> > > > > +	}
> > > > > +
> > > > > +	/* Wait for USB3 PHY internal SRAM initialization done */
> > > > > +	ret = readl_poll_timeout(aspeed_phy->regs + PHY3S00, val,
> > > > > +				 val & PHY3S00_INIT_DONE,
> > > > > +				 USEC_PER_MSEC, 10 * USEC_PER_MSEC);
> > > > > +	if (ret) {
> > > > > +		dev_err(aspeed_phy->dev, "SRAM init timeout\n");
> > > > > +		goto err_assert_reset;
> > > > > +	}
> > > > > +
> > > > > +	val = readl(aspeed_phy->regs + PHY3S00);
> > > > > +	val |= PHY3S00_SRAM_BYPASS;
> > > > > +	writel(val, aspeed_phy->regs + PHY3S00);
> > > >
> > > > According to the datasheet PHY3S00[15] (PHY3S00_INIT_DONE above)
> > > > indicates that the PHY internal SRAM initialisation is complete.
> > > > The datasheet reports the SRAM is used for configuration of
> > > > calibration among
> > other things.
> > > > PHY3S00[6] instructs the PHY that software has completed loading
> > > > the configuration data into SRAM, however PHY3S00_SRAM_BYPASS
> > > > (PHY3S00[7]) tells the PHY to load configuration from "hard wired" values.
> > > >
> > > > Is it necessary to wait for SRAM initialisation to complete if
> > > > we're
> > bypassing it?
> > > > Or are there other side-effects involved in the setting of PHY3S00[15]?
> > >
> > > Yes, it is necessary to wait SRAM initial, the driver polls PHY3S00[15].
> > > It reports that the boot loader in the PCS has finished initialising
> > > the SRAM (loading the contents into the PCS), and that
> > > initialisation has to complete before sram_bypass (PHY3S00[7]) may be
> asserted.
> > >
> >
> > Can you improve the comment then to make it clear that the wait is
> > necessary despite the bypass?
Hello Andrew,

Sorry for late response, it takes times commentate with our designer.
The PHY takes its configuration from the internal SRAM in both modes, so
the wait is necessary either way. PHY3S00[15] reports that the PCS boot
loader has finished initialising that SRAM, and the loading controls -
PHY3S00[7] and PHY3S00[6] - may only be driven once it has.

What the two controls select is which configuration is used:

  PHY3S00_SRAM_BYPASS   (bit 7)  the default design configuration
  PHY3S00_SRAM_EXT_LOAD (bit 6)  the ROM code configuration

After confirm with designer I will modify at v4 patch from SRAM_BYPASS
to EXT_LOAD, Due to that will be more precise configuration.

And I will update commit message with following.

    phy: aspeed: Add AST2700 USB3.2 PHY driver

    Add a driver for the USB3.2 PHY on the Aspeed AST2700, which is
    paired with the DWC3 controller.

    The PHY draws its configuration from an internal SRAM in both of the
    available modes, so the driver must wait for PHY3S00_INIT_DONE
    before selecting one. PHY3S00_SRAM_BYPASS selects the default design
    configuration and PHY3S00_SRAM_EXT_LOAD the ROM code configuration;
    the driver uses the latter.