Re: [PATCH v2] PCI: qcom: Block accesses to downstream devices on link down

From: Manivannan Sadhasivam

Date: Fri Sep 11 2026 - 02:23:07 EST


On Tue, Sep 08, 2026 at 06:00:30PM -0500, Bjorn Helgaas wrote:
> On Wed, Aug 19, 2026 at 11:36:54PM -0700, Qiang Yu wrote:
> > After a PCIe link goes down, software may still access the BAR (MMIO)
> > space or configuration space of devices behind that link before recovery
> > has run. As the link is down, these accesses never complete, resulting in
> > a storm of Completion Timeout AERs.
>
> What is special about qcom here? It seems like the Completion
> Timeouts and AER interrupts should happen with every PCIe controller.
>

The special behavior which is common across many (not all) ARM SoCs is that they
don't synthesize all-one response for completion timeouts, unlike RCs in x86
machines. Rather, they return AXI error response, resulting in CPU treating
them as SError, in-addition to AER storm.

Commit message missed mentioning SError though.

> Is this mitigating an issue that will still happen on other
> controllers and should be solved elsewhere, e.g., by changing the
> software that accesses the BAR to look for the error responses it gets
> when the Completion Timeout happens?
>

That would be too late as we don't get a proper error response. That's why this
patch is used.

> The patch refers to the ECAM blocker (which I assume affects config
> accesses) and doesn't mention MMIO. Is the SLV_AXI stuff for MMIO?
>

ECAM blocker is a Qcom's custom implementation which prevents the config access
to go out of the link and terminate the request properly. And yes, it doesn't
affect MMIO like BAR.

> Assume the root port leads to a switch, and the switch has two links
> to downstream devices. If one of the switch downstream links goes
> down, is this going to kill the device on the other link that is still
> up?
>

ECAM blocker is only enabled when the PCIe link to the Root Port goes down. We
don't get LDn interrupt when the switch downstream link goes down. In that case,
the switch should synthesize the error response if the CPU tries to access the
unavailable device.

- Mani

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