[PATCH 3/5] arm64: dts: qcom: nord-embedded: Add USB resources and PHYs
From: Shawn Guo
Date: Fri Sep 11 2026 - 10:31:15 EST
From: Bartosz Golaszewski <bartosz.golaszewski@xxxxxxxxxxxxxxxx>
Add the platform resources for the three USB controllers on the embedded
Nord variant: clocks, resets, power domains and interconnect paths.
Add the eUSB2 PHY for each of the three controllers, plus the QMP combo
PHYs for USB_0 and USB_1, and feed the two QMP USB3 pipe clocks back
into negcc, which so far carried placeholder zeros in their place.
The eUSB2 PHY of instance 2 gets no 'resets': the SoC provides only two
QUSB2PHY block resets, belonging to instances 0 and 1. Instance 2 comes
out of reset with the rest of the USB20 tile, driven by the controller.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@xxxxxxxxxxxxxxxx>
Signed-off-by: Shawn Guo <shengchao.guo@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 307 +++++++++++++++++++-
1 file changed, 305 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
index c7ac2e66632e..84ce57a07361 100644
--- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
+++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
@@ -11,6 +11,7 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,nord-rpmh.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -842,6 +843,162 @@ hpass_ag_noc: interconnect@5fc0000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ usb_2_hsphy: phy@88e0000 {
+ compatible = "qcom,nord-snps-eusb2-phy",
+ "qcom,sm8550-snps-eusb2-phy";
+ reg = <0x0 0x088e0000 0x0 0x154>;
+
+ clocks = <&tcsrcc TCSR_USB2_2_CLKREF_EN>;
+ clock-names = "ref";
+
+ /*
+ * The SoC has three eUSB2 PHYs but only two QUSB2PHY block
+ * resets, which belong to instances 0 and 1 (usb_0 and usb_1).
+ * This PHY, instance 2, has none of its own: it is taken out of
+ * reset together with the rest of the USB20 tile by
+ * NE_GCC_USB20_PRIM_BCR, which the controller owns and pulses
+ * before touching any register. So no 'resets' here - both
+ * consumers would need that single reset exclusively.
+ */
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_0_qmpphy: phy@88e1000 {
+ compatible = "qcom,nord-qmp-usb3-dp-phy";
+ reg = <0x0 0x088e1000 0x0 0x3000>;
+
+ clocks = <&negcc NE_GCC_USB3_PRIM_PHY_AUX_CLK>,
+ <&tcsrcc TCSR_USB3_0_CLKREF_EN>,
+ <&negcc NE_GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&negcc NE_GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "com_aux",
+ "usb3_pipe";
+
+ power-domains = <&negcc NE_GCC_USB3_PHY_GDSC>;
+
+ resets = <&negcc NE_GCC_USB3_PHY_PRIM_BCR>,
+ <&negcc NE_GCC_USB3_DP_PHY_PRIM_BCR>;
+ reset-names = "phy",
+ "common";
+
+ #clock-cells = <1>;
+ #phy-cells = <1>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb_0_qmpphy_usb_ss_out: endpoint@1 {
+ reg = <1>;
+ data-lanes = <1 0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_0_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_0_dwc3_ss>;
+ };
+ };
+ };
+ };
+
+ usb_1_qmpphy: phy@88e4000 {
+ compatible = "qcom,nord-qmp-usb3-dp-phy";
+ reg = <0x0 0x088e4000 0x0 0x3000>;
+
+ clocks = <&negcc NE_GCC_USB3_SEC_PHY_AUX_CLK>,
+ <&tcsrcc TCSR_USB3_1_CLKREF_EN>,
+ <&negcc NE_GCC_USB3_SEC_PHY_COM_AUX_CLK>,
+ <&negcc NE_GCC_USB3_SEC_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "com_aux",
+ "usb3_pipe";
+
+ power-domains = <&negcc NE_GCC_USB3_SEC_PHY_GDSC>;
+
+ resets = <&negcc NE_GCC_USB3_PHY_SEC_BCR>,
+ <&negcc NE_GCC_USB3_DP_PHY_SEC_BCR>;
+ reset-names = "phy",
+ "common";
+
+ #clock-cells = <1>;
+ #phy-cells = <1>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Same as usb_0_qmpphy above. */
+ usb_1_qmpphy_usb_ss_out: endpoint@1 {
+ reg = <1>;
+ data-lanes = <1 0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_ss>;
+ };
+ };
+ };
+ };
+
+ usb_0_hsphy: phy@88ea000 {
+ compatible = "qcom,nord-snps-eusb2-phy",
+ "qcom,sm8550-snps-eusb2-phy";
+ reg = <0x0 0x088ea000 0x0 0x154>;
+
+ clocks = <&tcsrcc TCSR_USB2_0_CLKREF_EN>;
+ clock-names = "ref";
+
+ resets = <&negcc NE_GCC_QUSB2PHY_PRIM_BCR>;
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_1_hsphy: phy@88eb000 {
+ compatible = "qcom,nord-snps-eusb2-phy",
+ "qcom,sm8550-snps-eusb2-phy";
+ reg = <0x0 0x088eb000 0x0 0x154>;
+
+ clocks = <&tcsrcc TCSR_USB2_1_CLKREF_EN>;
+ clock-names = "ref";
+
+ resets = <&negcc NE_GCC_QUSB2PHY_SEC_BCR>;
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
negcc: clock-controller@8900000 {
compatible = "qcom,nord-negcc";
reg = <0x0 0x08900000 0x0 0xf4200>;
@@ -850,8 +1007,8 @@ negcc: clock-controller@8900000 {
<0>,
<0>,
<0>,
- <0>,
- <0>;
+ <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
+ <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
@@ -1881,3 +2038,149 @@ opp-403000000 {
};
};
};
+
+&usb_0 {
+ clocks = <&negcc NE_GCC_CNOC_USB3_PRIM_AXI_CLK>,
+ <&negcc NE_GCC_USB31_PRIM_MASTER_CLK>,
+ <&negcc NE_GCC_AGGRE_NOC_USB3_PRIM_AXI_CLK>,
+ <&negcc NE_GCC_USB31_PRIM_SLEEP_CLK>,
+ <&negcc NE_GCC_USB31_PRIM_MOCK_UTMI_CLK>,
+ <&tcsrcc TCSR_USB3_0_CLKREF_EN>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi",
+ "xo";
+
+ assigned-clocks = <&negcc NE_GCC_USB31_PRIM_MOCK_UTMI_CLK>,
+ <&negcc NE_GCC_USB31_PRIM_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+
+ power-domains = <&negcc NE_GCC_USB31_PRIM_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ resets = <&negcc NE_GCC_USB31_PRIM_BCR>;
+
+ interconnects = <&aggre1_noc_tile MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "usb-ddr",
+ "apps-usb";
+
+ phys = <&usb_0_hsphy>,
+ <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>;
+ phy-names = "usb2-phy",
+ "usb3-phy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_0_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_0_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_0_qmpphy_usb_ss_in>;
+ };
+ };
+ };
+};
+
+&usb_1 {
+ clocks = <&negcc NE_GCC_CNOC_USB3_SEC_AXI_CLK>,
+ <&negcc NE_GCC_USB31_SEC_MASTER_CLK>,
+ <&negcc NE_GCC_AGGRE_NOC_USB3_SEC_AXI_CLK>,
+ <&negcc NE_GCC_USB31_SEC_SLEEP_CLK>,
+ <&negcc NE_GCC_USB31_SEC_MOCK_UTMI_CLK>,
+ <&tcsrcc TCSR_USB3_1_CLKREF_EN>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi",
+ "xo";
+
+ assigned-clocks = <&negcc NE_GCC_USB31_SEC_MOCK_UTMI_CLK>,
+ <&negcc NE_GCC_USB31_SEC_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+
+ power-domains = <&negcc NE_GCC_USB31_SEC_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ resets = <&negcc NE_GCC_USB31_SEC_BCR>;
+
+ interconnects = <&aggre1_noc_tile MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "usb-ddr",
+ "apps-usb";
+
+ phys = <&usb_1_hsphy>,
+ <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
+ phy-names = "usb2-phy",
+ "usb3-phy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
+ };
+ };
+ };
+};
+
+&usb_2 {
+ clocks = <&negcc NE_GCC_CNOC_USB2_AXI_CLK>,
+ <&negcc NE_GCC_USB20_MASTER_CLK>,
+ <&negcc NE_GCC_AGGRE_NOC_USB2_AXI_CLK>,
+ <&negcc NE_GCC_USB20_SLEEP_CLK>,
+ <&negcc NE_GCC_USB20_MOCK_UTMI_CLK>,
+ <&tcsrcc TCSR_USB2_2_CLKREF_EN>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi",
+ "xo";
+
+ assigned-clocks = <&negcc NE_GCC_USB20_MOCK_UTMI_CLK>,
+ <&negcc NE_GCC_USB20_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <120000000>;
+
+ power-domains = <&negcc NE_GCC_USB20_PRIM_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ resets = <&negcc NE_GCC_USB20_PRIM_BCR>;
+
+ interconnects = <&aggre1_noc_tile MASTER_USB2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "usb-ddr",
+ "apps-usb";
+
+ phys = <&usb_2_hsphy>;
+ phy-names = "usb2-phy";
+};
--
2.43.0