Re: [PATCH v3 1/4] arm64: dts: renesas: r9a08g046: Add USB2.0 host/phy device nodes

[Geert Uytterhoeven]

Hi Tommaso, Biju,

On Wed, 9 Sept 2026 at 10:55, Tommaso Merciai
<tommaso.merciai.xr@xxxxxxxxxxxxxx> wrote:
> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
>
> Add USB2.0 device nodes to the RZ/G3L (r9a08g046) SoC DTSI, covering
> the USB PHY controller, OHCI/EHCI host controllers, and USB2 PHYs for
> both ports.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@xxxxxxxxxxxxxx>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi

> +               usb2_phy0: usb-phy@11e10200 {
> +                       compatible = "renesas,usb2-phy-r9a08g046";
> +                       reg = <0 0x11e10200 0 0x700>;
> +                       interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&cpg CPG_MOD R9A08G046_USB_PCLK>,
> +                                <&cpg CPG_MOD R9A08G046_USB_U2H0_HCLK>;

No clock-names, while other SoCs using the same bindings do have it?

> +                       resets = <&phyrst 0>,
> +                                <&cpg R9A08G046_USB_U2H0_HRESETN>;
> +                       #phy-cells = <1>;
> +                       power-domains = <&cpg>;
> +                       status = "disabled";
> +               };
> +
> +               usb2_phy1: usb-phy@11e90200 {
> +                       compatible = "renesas,usb2-phy-r9a08g046";
> +                       reg = <0 0x11e90200 0 0x700>;
> +                       interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&cpg CPG_MOD R9A08G046_USB_PCLK>,
> +                                <&cpg CPG_MOD R9A08G046_USB_U2H1_HCLK>;

Likewise.

> +                       resets = <&phyrst 1>,
> +                                <&cpg R9A08G046_USB_U2H1_HRESETN>;
> +                       #phy-cells = <1>;
> +                       power-domains = <&cpg>;
> +                       status = "disabled";
> +               };
> +
>                 pcie: pcie@11e40000 {
>                         reg = <0 0x11e40000 0 0x10000>;
>                         ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>;

Looks like U2H[01]_INT and U2H[01]_WAKEON_INT are missing,
but they are also not listed in the DT bindings?

The rest LGTM.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds