[PATCH bpf-next 0/5] bpf, x86: Extend CPUv4 instruction support in the i386 JIT

[Nicholas Dudar]

Add MOVSX, MEMSX, 32-bit-offset unconditional jumps and unconditional
byte swaps to the i386 JIT. MOVSX currently produces ordinary moves;
the other instructions are rejected by the backend.

The load-emitter extraction is separate from MEMSX so the code movement
and signed-load handling can be reviewed independently. MOVSX comes first
because context-access conversion can lower signed loads into ordinary
loads followed by MOVSX.

The separately posted i386 SDIV/SMOD work is independent of this series:
https://lore.kernel.org/bpf/20260731002950.179573-1-main.kalliope@xxxxxxxxx/

Tested on QEMU i386 with CONFIG_BPF_JIT_ALWAYS_ON=y. The full test_bpf
suite improves from 845/216 to 862/199 pass/fail: the 17 newly passing
cases cover these instructions, with no other result changes. Additional
verifier-loaded programs check full-width results and ordinary controls.

Of the remaining 199 failures, 8 are ALU32 SDIV/SMOD result mismatches.
The other 191 fail during program creation or runtime selection: 149
atomic cases, 37 ALU64 division/modulo cases (including a mixed ALU test),
4 long conditional jumps and 1 jump/gap stress case.

All five intermediate JIT objects build. A standalone emission harness
checks ordinary-load byte equivalence across the extraction and compares
MOVSX staging with the earlier emitter, accounting for the removed
self-moves. No physical hardware was tested.

Nicholas Dudar (5):
  bpf, x86: Add support for BPF_MOVSX in the i386 JIT
  bpf, x86: Extract the i386 JIT load emitter
  bpf, x86: Add BPF_MEMSX support to the i386 JIT
  bpf, x86: Add BPF_JMP32 | BPF_JA support to the i386 JIT
  bpf, x86: Add unconditional byte swap to the i386 JIT

 arch/x86/net/bpf_jit_comp32.c | 227 ++++++++++++++++++++++++----------
 1 file changed, 161 insertions(+), 66 deletions(-)


base-commit: 29fcf9ce4bbdf4cc339def776860e1c0095bca98