Re: [PATCHv2] gpio: mvebu: keep resume masks within the irqchip cache

[Sebastian Andrzej Siewior]

On 2026-09-15 15:24:24 [-0700], Rosen Penev wrote:
> On Mon, Sep 14, 2026 at 11:43 PM Sebastian Andrzej Siewior
> <bigeasy@xxxxxxxxxxxxx> wrote:
> >
> > On 2026-09-14 17:44:06 [-0700], Rosen Penev wrote:
> > > mvebu_gpio_resume() writes the edge/level mask registers saved at
> > > suspend time straight back to hardware, bypassing the irqchip's
> > > mask_cache_priv.  genirq skips mask_irq() for a line it already
> > > considers masked, so restoring a bit in hardware that genirq thinks
> > > is still masked leaves that line unmasked behind genirq's back.  An
> > > asserted level line then has nobody to ack it, and the moment
> > > interrupts are re-enabled the chained handler storms, hanging resume.
> >
> > Why is the mask value changed after suspend?
> In order to keep genirq and the hardware in sync.

There seems to be write after suspend took place or before resume.

Sebastian