[PATCH] pinctrl: qcom: nord: fix GPIO interrupt target width

[Zhangfei Gao]

The TARGET_PROC field in the Nord GPIO_INTR_CFG registers occupies bits
11:8. Describe it as four bits wide so the common Qualcomm pinctrl code
clears the complete field before routing an interrupt to the application
processor.

Without intr_target_width, the common code uses its three-bit default
mask. Since GPIO_INTR_CFG resets with TARGET_PROC set to 0xf (NONE), bit
11 remains set when the driver programs HMSS target 3. The resulting
target is 0xb (HPASS_DSP_1), observed as an interrupt configuration value
of 0xb1b instead of 0x31b.

The GPIO interrupt status is consequently latched, but the HMSS TLMM
summary interrupt at GIC SPI 208 is never asserted. This affects all Nord
GPIO interrupts using the TLMM summary path, including the Ethernet PHY
interrupts on GPIO55 and GPIO141.

Fixes: c24dd0826f06 ("pinctrl: qcom: add the TLMM driver for the Nord platforms")
Signed-off-by: Zhangfei Gao <zhangfei.gao@xxxxxxxxxxxxxxxx>
---
 drivers/pinctrl/qcom/pinctrl-nord.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pinctrl/qcom/pinctrl-nord.c b/drivers/pinctrl/qcom/pinctrl-nord.c
index 7f37f8e819ba..010760cf0bf5 100644
--- a/drivers/pinctrl/qcom/pinctrl-nord.c
+++ b/drivers/pinctrl/qcom/pinctrl-nord.c
@@ -32,6 +32,7 @@
 		.intr_wakeup_present_bit = 6,                         \
 		.intr_wakeup_enable_bit = 7,                          \
 		.intr_target_bit = 8,                                 \
+		.intr_target_width = 4,                               \
 		.intr_target_kpss_val = 3,                            \
 		.intr_raw_status_bit = 4,                             \
 		.intr_polarity_bit = 1,                               \
-- 
2.43.0