[PATCH v2 01/19] dt-bindings: clock: qcom: Add MSM8952 global clock controller

From: Muzaffer Kadir via B4 Relay

Date: Wed Sep 16 2026 - 10:41:28 EST

From: Muzaffer Kadir <muzafferkadir@xxxxxxxxxxxxxx>

Add a device tree binding to describe clocks, resets and power domains
provided by the global clock controller on MSM8952 SoC.

Signed-off-by: Muzaffer Kadir <muzafferkadir@xxxxxxxxxxxxxx>
---
.../bindings/clock/qcom,gcc-msm8952.yaml | 56 ++++++
include/dt-bindings/clock/qcom,gcc-msm8952.h | 217 +++++++++++++++++++++
2 files changed, 273 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8952.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8952.yaml
new file mode 100644
index 000000000000..274dde633e17
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8952.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8952.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller on MSM8952
+
+maintainers:
+ - Muzaffer Kadir <muzafferkadir@xxxxxxxxxxxxxx>
+
+description: |
+ Qualcomm global clock control module provides the clocks, resets and power
+ domains on MSM8952.
+
+ See also::
+ include/dt-bindings/clock/qcom,gcc-msm8952.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,gcc-msm8952
+
+ clocks:
+ items:
+ - description: XO source
+ - description: Always-on XO source
+ - description: DSI phy instance 0 dsi clock
+ - description: DSI phy instance 0 byte clock
+
+ clock-names:
+ items:
+ - const: xo
+ - const: xo_a
+ - const: dsi0pll
+ - const: dsi0pllbyte
+
+required:
+ - compatible
+ - '#power-domain-cells'
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ clock-controller@1800000 {
+ compatible = "qcom,gcc-msm8952";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ reg = <0x01800000 0x80000>;
+ };
+...
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8952.h b/include/dt-bindings/clock/qcom,gcc-msm8952.h
new file mode 100644
index 000000000000..fc592228675d
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-msm8952.h
@@ -0,0 +1,217 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright 2020 Linaro Limited
+ * Copyright 2026 Muzaffer Kadir <muzafferkadir@xxxxxxxxxxxxxx>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_8952_H
+#define _DT_BINDINGS_CLK_MSM_GCC_8952_H
+
+#define GPLL0 0
+#define GPLL0_VOTE 1
+#define GPLL3 2
+#define GPLL3_EARLY 3
+#define GPLL4 4
+#define GPLL4_VOTE 5
+#define GPLL6 6
+#define GPLL6_VOTE 7
+#define CAMSS_TOP_AHB_CLK_SRC 8
+#define APSS_AHB_CLK_SRC 9
+#define CSI0_CLK_SRC 10
+#define CSI1_CLK_SRC 11
+#define GFX3D_CLK_SRC 12
+#define VFE0_CLK_SRC 13
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC 14
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC 15
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC 16
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC 17
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC 18
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC 19
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC 20
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC 21
+#define BLSP1_UART1_APPS_CLK_SRC 22
+#define BLSP1_UART2_APPS_CLK_SRC 23
+#define CCI_CLK_SRC 24
+#define CAMSS_GP0_CLK_SRC 25
+#define CAMSS_GP1_CLK_SRC 26
+#define JPEG0_CLK_SRC 27
+#define MCLK0_CLK_SRC 28
+#define MCLK1_CLK_SRC 29
+#define CSI0PHYTIMER_CLK_SRC 30
+#define CSI1PHYTIMER_CLK_SRC 31
+#define CPP_CLK_SRC 32
+#define CRYPTO_CLK_SRC 33
+#define GP1_CLK_SRC 34
+#define GP2_CLK_SRC 35
+#define GP3_CLK_SRC 36
+#define BYTE0_CLK_SRC 37
+#define ESC0_CLK_SRC 38
+#define MDP_CLK_SRC 39
+#define PCLK0_CLK_SRC 40
+#define VSYNC_CLK_SRC 41
+#define PDM2_CLK_SRC 42
+#define SDCC1_APPS_CLK_SRC 43
+#define SDCC2_APPS_CLK_SRC 44
+#define USB_HS_SYSTEM_CLK_SRC 45
+#define VCODEC0_CLK_SRC 46
+#define GCC_BLSP1_AHB_CLK 47
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK 48
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK 49
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK 50
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK 51
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK 52
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK 53
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK 54
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK 55
+#define GCC_BLSP1_UART1_APPS_CLK 56
+#define GCC_BLSP1_UART2_APPS_CLK 57
+#define GCC_BOOT_ROM_AHB_CLK 58
+#define GCC_CAMSS_CCI_AHB_CLK 59
+#define GCC_CAMSS_CCI_CLK 60
+#define GCC_CAMSS_CSI0_AHB_CLK 61
+#define GCC_CAMSS_CSI0_CLK 62
+#define GCC_CAMSS_CSI0PHY_CLK 63
+#define GCC_CAMSS_CSI0PIX_CLK 64
+#define GCC_CAMSS_CSI0RDI_CLK 65
+#define GCC_CAMSS_CSI1_AHB_CLK 66
+#define GCC_CAMSS_CSI1_CLK 67
+#define GCC_CAMSS_CSI1PHY_CLK 68
+#define GCC_CAMSS_CSI1PIX_CLK 69
+#define GCC_CAMSS_CSI1RDI_CLK 70
+#define GCC_CAMSS_CSI_VFE0_CLK 71
+#define GCC_CAMSS_GP0_CLK 72
+#define GCC_CAMSS_GP1_CLK 73
+#define GCC_CAMSS_ISPIF_AHB_CLK 74
+#define GCC_CAMSS_JPEG0_CLK 75
+#define GCC_CAMSS_JPEG_AHB_CLK 76
+#define GCC_CAMSS_JPEG_AXI_CLK 77
+#define GCC_CAMSS_MCLK0_CLK 78
+#define GCC_CAMSS_MCLK1_CLK 79
+#define GCC_CAMSS_MICRO_AHB_CLK 80
+#define GCC_CAMSS_CSI0PHYTIMER_CLK 81
+#define GCC_CAMSS_CSI1PHYTIMER_CLK 82
+#define GCC_CAMSS_AHB_CLK 83
+#define GCC_CAMSS_TOP_AHB_CLK 84
+#define GCC_CAMSS_CPP_AHB_CLK 85
+#define GCC_CAMSS_CPP_CLK 86
+#define GCC_CAMSS_VFE0_CLK 87
+#define GCC_CAMSS_VFE0_AHB_CLK 88
+#define GCC_CAMSS_VFE0_AXI_CLK 89
+#define GCC_CRYPTO_AHB_CLK 90
+#define GCC_CRYPTO_AXI_CLK 91
+#define GCC_CRYPTO_CLK 92
+#define GCC_OXILI_GMEM_CLK 93
+#define GCC_GP1_CLK 94
+#define GCC_GP2_CLK 95
+#define GCC_GP3_CLK 96
+#define GCC_MDSS_AHB_CLK 97
+#define GCC_MDSS_AXI_CLK 98
+#define GCC_MDSS_BYTE0_CLK 99
+#define GCC_MDSS_ESC0_CLK 100
+#define GCC_MDSS_MDP_CLK 101
+#define GCC_MDSS_PCLK0_CLK 102
+#define GCC_MDSS_VSYNC_CLK 103
+#define GCC_MSS_CFG_AHB_CLK 104
+#define GCC_OXILI_AHB_CLK 105
+#define GCC_OXILI_GFX3D_CLK 106
+#define GCC_PDM2_CLK 107
+#define GCC_PDM_AHB_CLK 108
+#define GCC_PRNG_AHB_CLK 109
+#define GCC_SDCC1_AHB_CLK 110
+#define GCC_SDCC1_APPS_CLK 111
+#define GCC_SDCC2_AHB_CLK 112
+#define GCC_SDCC2_APPS_CLK 113
+#define GCC_GTCU_AHB_CLK 114
+#define GCC_JPEG_TBU_CLK 115
+#define GCC_MDP_TBU_CLK 116
+#define GCC_SMMU_CFG_CLK 117
+#define GCC_VENUS_TBU_CLK 118
+#define GCC_VFE_TBU_CLK 119
+#define GCC_USB2A_PHY_SLEEP_CLK 120
+#define GCC_USB_HS_AHB_CLK 121
+#define GCC_USB_HS_SYSTEM_CLK 122
+#define GCC_VENUS0_AHB_CLK 123
+#define GCC_VENUS0_AXI_CLK 124
+#define GCC_VENUS0_VCODEC0_CLK 125
+#define GCC_APSS_TCU_CLK 126
+#define GCC_GFX_TCU_CLK 127
+#define GCC_BIMC_GFX_CLK 128
+#define GCC_BIMC_GPU_CLK 129
+#define GCC_MSS_Q6_BIMC_AXI_CLK 130
+#define GCC_GFX_TBU_CLK 131
+#define GCC_CPP_TBU_CLK 132
+#define USB_FS_SYSTEM_CLK_SRC 133
+#define USB_FS_IC_CLK_SRC 134
+#define GCC_USB_FS_AHB_CLK 135
+#define GCC_USB_FS_IC_CLK 136
+#define GCC_USB_FS_SYSTEM_CLK 137
+#define GCC_VENUS0_CORE0_VCODEC0_CLK 138
+#define GCC_VENUS0_CORE1_VCODEC0_CLK 139
+#define GCC_OXILI_TIMER_CLK 140
+#define GCC_USB_HS_PHY_CFG_AHB_CLK 141
+#define CSI2_CLK_SRC 142
+#define GCC_CAMSS_CSI2_AHB_CLK 143
+#define GCC_CAMSS_CSI2_CLK 144
+#define GCC_CAMSS_CSI2PHY_CLK 145
+#define GCC_CAMSS_CSI2PIX_CLK 146
+#define GCC_CAMSS_CSI2RDI_CLK 147
+#define SDCC1_ICE_CORE_CLK_SRC 148
+#define GCC_SDCC1_ICE_CORE_CLK 149
+#define BLSP2_QUP1_I2C_APPS_CLK_SRC 150
+#define BLSP2_QUP1_SPI_APPS_CLK_SRC 151
+#define BLSP2_QUP2_I2C_APPS_CLK_SRC 152
+#define BLSP2_QUP2_SPI_APPS_CLK_SRC 153
+#define BLSP2_QUP3_I2C_APPS_CLK_SRC 154
+#define BLSP2_QUP3_SPI_APPS_CLK_SRC 155
+#define BLSP2_QUP4_I2C_APPS_CLK_SRC 156
+#define BLSP2_QUP4_SPI_APPS_CLK_SRC 157
+#define BLSP2_UART1_APPS_CLK_SRC 158
+#define BLSP2_UART2_APPS_CLK_SRC 159
+#define GCC_BLSP2_AHB_CLK 160
+#define GCC_BLSP2_QUP1_I2C_APPS_CLK 161
+#define GCC_BLSP2_QUP1_SPI_APPS_CLK 162
+#define GCC_BLSP2_QUP2_I2C_APPS_CLK 163
+#define GCC_BLSP2_QUP2_SPI_APPS_CLK 164
+#define GCC_BLSP2_QUP3_I2C_APPS_CLK 165
+#define GCC_BLSP2_QUP3_SPI_APPS_CLK 166
+#define GCC_BLSP2_QUP4_I2C_APPS_CLK 167
+#define GCC_BLSP2_QUP4_SPI_APPS_CLK 168
+#define GCC_BLSP2_UART1_APPS_CLK 169
+#define GCC_BLSP2_UART2_APPS_CLK 170
+#define VFE1_CLK_SRC 171
+#define GCC_CAMSS_VFE1_CLK 172
+#define GCC_CAMSS_VFE1_AHB_CLK 173
+#define GCC_CAMSS_VFE1_AXI_CLK 174
+#define GCC_CAMSS_CSI_VFE1_CLK 175
+#define MCLK2_CLK_SRC 176
+#define GCC_CAMSS_MCLK2_CLK 177
+#define GCC_VFE1_TBU_CLK 178
+#define GCC_IPA_TBU_CLK 179
+#define GCC_CAMSS_CPP_AXI_CLK 180
+
+/* Indexes for GDSCs */
+#define VENUS_GDSC 0
+#define MDSS_GDSC 1
+#define JPEG_GDSC 2
+#define VFE0_GDSC 3
+#define VFE1_GDSC 4
+#define OXILI_GX_GDSC 5
+#define VENUS_CORE0_GDSC 6
+#define VENUS_CORE1_GDSC 7
+#define CPP_GDSC 8
+
+/* Indexes for Resets */
+#define RST_CAMSS_MICRO_BCR 0
+#define RST_USB_HS_BCR 1
+#define RST_QUSB2_PHY_BCR 2
+#define RST_USB2_HS_PHY_ONLY_BCR 3
+#define RST_USB_HS_PHY_CFG_AHB_CBCR 4
+#define RST_USB_FS_BCR 5
+#define RST_CAMSS_CSI1PIX_CBCR 6
+#define RST_CAMSS_CSI_VFE1_CBCR 7
+#define RST_CAMSS_VFE1_CBCR 8
+#define RST_CAMSS_CPP_CBCR 9
+#define RST_MSS_BCR 10
+#define RST_MDSS_BCR 11
+
+#endif

--
2.55.0