Re: [PATCH 3/5] arm64: dts: qcom: glymur: Add UFS nodes

[Pradeep Pragallapati]

On 9/14/2026 2:44 PM, Konrad Dybcio wrote:
> On 9/11/26 6:47 PM, Pradeep P V K wrote:
> > Add UFS PHY and UFS host controller nodes for Glymur SoC.
> >
> > Signed-off-by: Pradeep P V K <pradeep.pragallapati@xxxxxxxxxxxxxxxx>
> > ---
> >   arch/arm64/boot/dts/qcom/glymur.dtsi | 114 ++++++++++++++++++++++++++++++++++-
> >   1 file changed, 111 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > index 624a9edd602c..7bbc804ed340 100644
> > --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > @@ -812,9 +812,9 @@ gcc: clock-controller@100000 {
> >   				 <0>,				/* QUSB4 1 PHY RX 1 */
> >   				 <0>,				/* QUSB4 2 PHY RX 0 */
> >   				 <0>,				/* QUSB4 2 PHY RX 1 */
> > -				 <0>,				/* UFS PHY RX Symbol 0 */
> > -				 <0>,				/* UFS PHY RX Symbol 1 */
> > -				 <0>,				/* UFS PHY TX Symbol 0 */
> > +				 <&ufs_mem_phy 0>,		/* UFS PHY RX Symbol 0 */
> > +				 <&ufs_mem_phy 1>,		/* UFS PHY RX Symbol 1 */
> > +				 <&ufs_mem_phy 2>,		/* UFS PHY TX Symbol 0 */
>
> The comment is no useful, please drop it
sure, i will remove it in my next patchset.>
> >   				 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
> >   				 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
> >   				 <&usb_2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
> > @@ -4103,6 +4103,114 @@ rng: rng@10c3000 {
> >   			reg = <0x0 0x010c3000 0x0 0x1000>;
> >   		};
> >   
> > +		ufs_mem_phy: phy@1d80000 {
> > +			compatible = "qcom,glymur-qmp-ufs-phy";
> > +			reg = <0x0 0x01d80000 0x0 0x2000>;
> > +
> > +			clocks = <&rpmhcc RPMH_CXO_CLK>,
> > +				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
> > +				 /* UFS and PCIE4 shares the same clkref on glymur */
>
> s/shares/share
ok, i will change this in my next patchset.>
> > +				 <&tcsr TCSR_PCIE_4_CLKREF_EN>;
> > +
> > +			clock-names = "ref",
> > +				      "ref_aux",
> > +				      "qref";
> > +
> > +			resets = <&ufs_mem_hc 0>;
> > +			reset-names = "ufsphy";
> > +
> > +			#clock-cells = <1>;
> > +			#phy-cells = <0>;
> > +
> > +			status = "disabled";
> > +		};
> > +
> > +		ufs_mem_hc: ufshc@1d84000 {
> > +			compatible = "qcom,glymur-ufshc",
> > +				     "qcom,ufshc",
> > +				     "jedec,ufs-2.0";
> > +			reg = <0x0 0x01d84000 0x0 0x3000>,
> > +			      <0x0 0x01da0000 0x0 0x15000>;
> > +
> > +			reg-names = "std",
>
> Stray \n above
sure, will remove it in my next patchset version.
> [...]
>
> > +			ufs_opp_table: opp-table {
> > +				compatible = "operating-points-v2";
> > +
> > +				opp-100000000 {
> > +					opp-hz = /bits/ 64 <100000000>,
> > +						 /bits/ 64 <0>,
> > +						 /bits/ 64 <0>,
> > +						 /bits/ 64 <100000000>,
> > +						 /bits/ 64 <0>,
> > +						 /bits/ 64 <0>,
> > +						 /bits/ 64 <0>,
> > +						 /bits/ 64 <0>;
> > +					required-opps = <&rpmhpd_opp_low_svs>;
> > +				};
> > +
> > +				opp-403000000 {
>
> There's another (201.5 MHz) OPP at SVS
acknowledged, i will add it in my next patchset.
> Konrad