Re: [PATCH] clk: qcom: gcc-ipq5424: Fix TME reset register offsets

[Kathiravan Thirumoorthy]

On 9/16/2026 4:59 PM, Abel Vesa wrote:
> The GCC_TME_BCR and GCC_TME_SEC_BUS_BCR offsets exceed the regmap maximum
> of 0x3f024. Regmap therefore rejects accesses to both registers, leaving
> the resets ineffective while the reset operations report success.
>
> The offsets appear to contain typographical errors. Use 0x10000 for
> GCC_TME_BCR, matching the offset used on IPQ9574 and the surrounding
> register layout. Use 0x1a030 for GCC_TME_SEC_BUS_BCR, placing it in the
> same register block as GCC_SEC_CTRL_BCR at 0x1a000.
>
> Fixes: 21b5d5a4a311 ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5424 SoC")
> Assisted-by: LLM
> Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxxxxxxxx>
> ---
> The replacement offsets are inferred from the register layout and the
> IPQ9574 driver;
>
> Sricharan, could you please confirm both offsets, particularly 0x1a030
> for GCC_TME_SEC_BUS_BCR?

Abel, I confirm that both offsets are correct and matching with HW doc. So,

Reviewed-by: Kathiravan Thirumoorthy 
<kathiravan.thirumoorthy@xxxxxxxxxxxxxxxx>