Re: [PATCH 03/17] dt-bindings: display/msm: Document Nord MDSS
From: Nabige Aala
Date: Thu Sep 17 2026 - 01:43:04 EST
On 9/17/2026 7:06 AM, Shawn Guo wrote:
On Fri, Sep 11, 2026 at 09:06:34PM +0530, Nabige Aala wrote:
From: Mahadevan P <mahadevan.p@xxxxxxxxxxxxxxxx>The DTS in downstream repository doesn't seem to agree. There is two
Add the binding for the display subsystem (MDSS) found on the Qualcomm
Nord SoC. Nord is MDSS 12.1, DP-only (no DSI), with two independent DP
controllers.
Signed-off-by: Mahadevan P <mahadevan.p@xxxxxxxxxxxxxxxx>
Signed-off-by: Nabige Aala <nabige.aala@xxxxxxxxxxxxxxxx>
---
.../bindings/display/msm/qcom,nord-mdss.yaml | 98 ++++++++++++++++++++++
1 file changed, 98 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,nord-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,nord-mdss.yaml
new file mode 100644
index 000000000000..0b0cacdca9db
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,nord-mdss.yaml
@@ -0,0 +1,98 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,nord-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Nord display subsystem (MDSS)
+
+maintainers:
+ - Mahadevan P <mahadevan.p@xxxxxxxxxxxxxxxx>
+
+description:
+ Nord display subsystem consists of MDSS (display controller), DPU 1499A
+ (display processing unit), and display interface controllers (DP only, no DSI).
+ This is MDSS 12.1, DP-only, with 2 independent DP controllers.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,nord-mdss
+
+ clocks:
+ items:
+ - description: Display AHB
+ - description: Display hf AXI
+ - description: Display core
+
+ clock-names:
+ items:
+ - const: iface
+ - const: bus
+ - const: core
+
+ iommus:
+ maxItems: 1
items for iommus.
I checked the Nord IPCAT. the resulted SID is same for both the SID (i.e. 0x03e0) in downstream repository.
I think we should update the downstream DT and use a single SID entry.
+Please run dt_binding_check against mainline kernel where the header is
+ interconnects:
+ items:
+ - description: Interconnect path from mdp0 port to the data bus
+ - description: Interconnect path from CPU to the reg bus
+
+ interconnect-names:
+ items:
+ - const: mdp0-mem
+ - const: cpu-cfg
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ const: qcom,nord-dpu
+
+ "^displayport-controller@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ const: qcom,nord-dp
+
+ "^phy@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ const: qcom,nord-dp-phy
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-nord.h>
actually qcom,nord-dispcc.h.
Ack, I will update according to mainline kernel.
Thanks,
Nabige
Shawn
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ display-subsystem@ae00000 {
+ compatible = "qcom,nord-mdss";
+ reg = <0x0ae00000 0x1000>;
+ reg-names = "mdss";
+ power-domains = <&dispcc_gdsc>;
+ clocks = <&dispcc DISPCC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISPCC_MDSS_MDP_CLK>;
+ clock-names = "iface", "bus", "core";
+ resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ iommus = <&apps_smmu 0x800 0x420>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ };
--
2.34.1
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