[PATCH 02/10] clk: renesas: r8a78000: Add clock for FCPV and VSP for SCP FW SDKv4.36

[Paul Elder]

Add clocks for the FCPV{B,I,D} and VSP{B,I}. They each have one clock
from an option of two: a 1066MHz and a quarter-divided 266MHz. As we
already have support for the 266MHz one, add just those for now.

Signed-off-by: Paul Elder <paul.elder+renesas@xxxxxxxxxxxxxxxx>
---
 drivers/clk/renesas/r8a78000-cpg.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/renesas/r8a78000-cpg.c b/drivers/clk/renesas/r8a78000-cpg.c
index b820d09e1a195068debe8a6eea7a01c534a97b23..17792ff6ab8ae2f7eb5c8f7e3d581b43177e195d 100644
--- a/drivers/clk/renesas/r8a78000-cpg.c
+++ b/drivers/clk/renesas/r8a78000-cpg.c
@@ -326,6 +326,8 @@ static const struct clk_map_in r8a78000_cpg_fw_4_31_0[] = {
 	{ R8A78000_CPG_SGASYNCD16_PERW_BUS,	FIXED_CLK(66M) },
 	{ R8A78000_CPG_S0D4_PERE_MAIN,		FIXED_CLK(200M) },
 	{ R8A78000_CPG_MSOCK_PERW_BUS,		1667 },
+	{ R8A78000_CPG_SGD4_VIO_DP_TX,		FIXED_CLK(266M)},
+	{ R8A78000_CPG_SGD4_VIO_DP_OTHER,	FIXED_CLK(266M)},
 	{ -1 }
 };
 

-- 
2.47.3