Re: [PATCH] gpio: mvebu: fix Armada XP per-CPU mask register save/restore

[Rosen Penev]

On Thu, Sep 17, 2026 at 2:53 AM Bartosz Golaszewski <brgl@xxxxxxxxxx> wrote:
>
> On Tue, 15 Sep 2026 05:12:25 +0200, Rosen Penev <rosenp@xxxxxxxxx> said:
> > The Armada XP variant keeps the per-CPU edge/level mask registers in a
> > second I/O window (percpu_regs) rather than in the main GPIO window.
> > The suspend and resume paths however read and wrote them through
> > mvchip->regs with the per-CPU offsets, which hits the global
> > GPIO_EDGE_MASK / GPIO_LEVEL_MASK registers instead. Per-CPU mask state
> > was therefore lost across suspend/resume, so a level line could end up
> > unmasked behind genirq's back and trigger an interrupt storm once
> > interrupts are re-enabled.
> >
> > Use mvchip->percpu_regs for the Armada XP per-CPU mask registers in
> > both the suspend save and the resume restore paths, matching the
> > mask/unmask handlers and the probe-time masking.
> >
> > Fixes: b5b7b487431b ("gpio: mvebu: add suspend/resume support")
> > Cc: stable@xxxxxxxxxxxxxxx
> > Assisted-by: LLM
> > Signed-off-by: Rosen Penev <rosenp@xxxxxxxxx>
> > ---
>
> This doesn't apply on top of the earlier mvebu patch, can you rebase on top of
> gpio/for-current and resend, please?
This should have gone in first. I'll rebase.
>
> Bart