Re: [PATCH 05/10] arm64: renesas: r8a78000: Add VSP[BI] nodes
From: Laurent Pinchart
Date: Thu Sep 17 2026 - 21:22:18 EST
On Thu, Sep 17, 2026 at 09:04:44PM +0900, Paul Elder wrote:
> Add DT nodes for the VSPB and VSPI IP cores in the R-Car X5H Soc.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@xxxxxxxxxxxxxxxx>
> Signed-off-by: Paul Elder <paul.elder+renesas@xxxxxxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/renesas/r8a78000.dtsi | 99 +++++++++++++++++++++++++++++++
> 1 file changed, 99 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> index 2f8886f8b6545026397fd83969882f8c62afa9d3..f90b869579d384e3fc13d0a13625b7cddaac2868 100644
> --- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> @@ -1072,6 +1072,105 @@ fcpvb4: fcp@c503c000 {
> resets = <&mdlc_vio 0x106>;
> };
>
> + vspi0: vsp@c5080000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xc5080000 0 0x8000>;
> + interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
Same comment as for 04/10.
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@xxxxxxxxxxxxxxxx>
Tested-by: Laurent Pinchart <laurent.pinchart+renesas@xxxxxxxxxxxxxxxx>
> + power-domains = <&mdlc_vio 0x07 0xfe>;
> + resets = <&mdlc_vio 0xfe>;
> +
> + renesas,fcp = <&fcpvi0>;
> + };
> +
> + vspi1: vsp@c5088000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xc5088000 0 0x8000>;
> + interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
> + power-domains = <&mdlc_vio 0x07 0xff>;
> + resets = <&mdlc_vio 0xff>;
> +
> + renesas,fcp = <&fcpvi1>;
> + };
> +
> + vspi2: vsp@c5090000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xc5090000 0 0x8000>;
> + interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
> + power-domains = <&mdlc_vio 0x07 0x100>;
> + resets = <&mdlc_vio 0x100>;
> +
> + renesas,fcp = <&fcpvi2>;
> + };
> +
> + vspi3: vsp@c5098000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xc5098000 0 0x8000>;
> + interrupts = <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
> + power-domains = <&mdlc_vio 0x07 0x101>;
> + resets = <&mdlc_vio 0x101>;
> +
> + renesas,fcp = <&fcpvi3>;
> + };
> +
> + vspb0: vsp@c50c0000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xc50c0000 0 0x8000>;
> + interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
> + power-domains = <&mdlc_vio 0x07 0xf9>;
> + resets = <&mdlc_vio 0xf9>;
> +
> + renesas,fcp = <&fcpvb0>;
> + };
> +
> + vspb1: vsp@c50c8000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xc50c8000 0 0x8000>;
> + interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
> + power-domains = <&mdlc_vio 0x07 0xfa>;
> + resets = <&mdlc_vio 0xfa>;
> +
> + renesas,fcp = <&fcpvb1>;
> + };
> +
> + vspb2: vsp@c50d0000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xc50d0000 0 0x8000>;
> + interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
> + power-domains = <&mdlc_vio 0x07 0xfb>;
> + resets = <&mdlc_vio 0xfb>;
> +
> + renesas,fcp = <&fcpvb2>;
> + };
> +
> + vspb3: vsp@c50d8000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xc50d8000 0 0x8000>;
> + interrupts = <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
> + power-domains = <&mdlc_vio 0x07 0xfc>;
> + resets = <&mdlc_vio 0xfc>;
> +
> + renesas,fcp = <&fcpvb3>;
> + };
> +
> + vspb4: vsp@c50e0000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xc50e0000 0 0x8000>;
> + interrupts = <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
> + power-domains = <&mdlc_vio 0x07 0xfd>;
> + resets = <&mdlc_vio 0xfd>;
> +
> + renesas,fcp = <&fcpvb4>;
> + };
> +
> mdlc_cmnn: system-controller@ca410000 {
> compatible = "renesas,r8a78000-mdlc";
> reg = <0 0xca410000 0 0x1000>;
--
Regards,
Laurent Pinchart