Re: [PATCH v8 2/2] hwrng: starfive: rework clk/reset teardown order for JHB100

[Herbert Xu]

On Mon, Sep 07, 2026 at 11:16:03AM +0800, lianfeng.ouyang wrote:
> From: Lianfeng Ouyang <lianfeng.ouyang@xxxxxxxxxxxxxxxx>
> 
> Rework the StarFive TRNG driver to address hardware-specific requirements
>   for JHB100 SoC. To avoid reset-domain crossing glitches, the driver now
>   ensures clocks are gated before asserting reset during teardown for
>   JHB100, while JH7110 retains the original reset-first sequence.
> 
> Add per-compatible match data (struct starfive_trng_data) describing the
>   clock/reset teardown order, a new "starfive,jhb100-trng" compatible, and
>   select the ordering from it.
> 
> Fix the runtime-PM get/put balancing across the init/read/reseed/cleanup
>   paths, manage PM and the clk/reset teardown via devm so all error paths
>   unwind correctly, run the SEU-triggered reseed from a workqueue instead
>   of hard IRQ, and serialise the command sequences with a mutex.
> 
> Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@xxxxxxxxxxxxxxxx>
> ---
>  MAINTAINERS                          |   2 +-
>  drivers/char/hw_random/jh7110-trng.c | 297 +++++++++++++++++++++------
>  2 files changed, 239 insertions(+), 60 deletions(-)

Please take a look at

https://sashiko.dev/#/patchset/20260907031603.188483-1-lianfeng.ouyang%40starfivetech.com

Thanks,
-- 
Email: Herbert Xu <herbert@xxxxxxxxxxxxxxxxxxx>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt