[PATCH v2 0/2] Add Xilinx Versal NET SMMU CSR interrupt controller support

From: Tushar Nimkar

Date: Fri Sep 18 2026 - 02:40:53 EST


On Xilinx Versal NET, the ARM SMMUv3 EVENTQ, PRIQ and GERROR interrupts
are routed through a vendor-specific Control and Status Register (CSR)
block, where they must be enabled, cleared and acknowledged before being
forwarded to the parent GIC.
This series adds a small irqchip driver for the CSR block that chains to
the standard arm-smmu-v3 driver, so the generic SMMUv3 driver needs no
changes.
Patch 1 adds the DT binding.
Patch 2 adds the irqchip driver.

Changes in v2:
- Posted as a proper threaded series with a cover letter (v1 patches
went out individually).
- dt-bindings (Krzysztof):
- Dropped the irrelevant arm,smmu-v3 consumer node from the example.
- Dropped the unused "smmu_irq_csr" label from the example.
- Dropped the redundant "binding" from the patch subject.
- irqchip driver (Thomas):
- Aligned kernel-doc member descriptions and used "interrupt"
instead of "IRQ".
- Used guard(raw_spinlock)() in the mask/unmask/ack callbacks and
addressed the comments related to lock handling.
- Thomas suggested using devm-managed allocation and irqdomain APIs;
however, the driver is registered via IRQCHIP_DECLARE() and has no
associated struct device, so devm APIs cannot be used. This code is
left unchanged.

Link to v1:
https://lore.kernel.org/all/20260817105233.1557748-1-tushar.nimkar@xxxxxxx/
https://lore.kernel.org/all/20260817105251.1557770-1-tushar.nimkar@xxxxxxx/

Signed-off-by: Tushar Nimkar <tushar.nimkar@xxxxxxx>
---
Anirudha Sarangi (2):
dt-bindings: interrupt-controller: Add Xilinx Versal NET SMMU CSR
irqchip: Add Xilinx Versal NET SMMU CSR interrupt controller driver

.../xlnx,versal-net-smmu-csr.yaml | 75 +++++++
MAINTAINERS | 10 +
drivers/irqchip/Kconfig | 10 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-xilinx-smmu-csr.c | 216 +++++++++++++++++++++
5 files changed, 312 insertions(+)
---
base-commit: 0d9d0dbf2fddcff5859d623e90ca73c4054276e1
change-id: 20260917-smmu-changes-v2-9cf7435d6969

Best regards,
--
Tushar Nimkar <tushar.nimkar@xxxxxxx>